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1. 发明授权

US06469584B1 Phase-locked loop system and method using an auto-ranging, frequency sweep window voltage controlled oscillator 有权
标题翻译：锁相环系统和方法采用自动量程，频率扫描窗口压控振荡器
公开(公告)号：US06469584B1
公开(公告)日：2002-10-22
申请号：US09708819
申请日：2000-11-08
申请人： Mehmet M. Eker , Joseph J. Balardeta
发明人： Mehmet M. Eker , Joseph J. Balardeta
IPC分类号： H03L700
CPC分类号： H03L7/113 , H03L7/087 , H03L7/095 , H03L7/14 , H03L2207/06 , Y10S331/02
摘要： A system and method have been provided for a phase-locked loop (PLL) circuit to use a selectable VCO frequency range during the acquisition of a signal, with a larger VCO frequency sweep window once the signal is being tracked. The circuit uses a frequency detector during acquisition, and the VCO is limited to operation is a plurality of discrete frequency bands. Each frequency band is sequentially searched using the low VCO gain. Upon acquisition, the frequency band is locked in, a phase detector is utilized, and the VCO sweep window is increased for tracking purposes.
摘要翻译：已经提供了一种用于锁相环（PLL）电路的系统和方法，以便在获取信号期间使用可选的VCO频率范围，一旦跟踪信号，则具有较大的VCO频率扫描窗口。该电路在采集期间使用频率检测器，并且VCO被限制为操作是多个离散频带。使用低VCO增益顺序地搜索每个频带。在获取时，锁定频带，利用相位检测器，并且为了跟踪目的而增加VCO扫描窗口。

2. 发明授权

US07327672B1 Signal routing in a node of a 1:N automatic protection switching network 有权
标题翻译： 1：N自动保护倒换网络节点信号路由
公开(公告)号：US07327672B1
公开(公告)日：2008-02-05
申请号：US10356167
申请日：2003-01-31
申请人： Simon S. Pang , Joseph J. Balardeta
发明人： Simon S. Pang , Joseph J. Balardeta
IPC分类号： G06F11/00
CPC分类号： H04J3/085
摘要： Automatic protection switching is implemented by channel devices in a data communication system node. Each channel devices includes input and output ports, a data receive port, a data send port, and a signal routing arrangement controlled by a processor element. The signal routing arrangement routes data between the channel devices such that, in the event of a channel failure, one channel device functions as a protection channel device. In a normal operating mode, each channel device routes data from its data receive port to its data send port, and routes data from its input port to its output port. In a protection mode, the protection channel device (and the protected channel device) routes data from its data receive port to its output port, and routes data from its input port to its data send port, while the remaining working channel devices function in the normal operating mode.
摘要翻译：自动保护切换由数据通信系统节点中的信道设备实现。每个通道设备包括输入和输出端口，数据接收端口，数据发送端口和由处理器元件控制的信号路由布置。信号路由布置在信道设备之间路由数据，使得在信道故障的情况下，一个信道设备用作保护信道设备。在正常工作模式下，每个通道设备将数据从其数据接收端口路由到其数据发送端口，并将数据从其输入端口路由到其输出端口。在保护模式下，保护通道设备（和受保护通道设备）将数据从其数据接收端口路由到其输出端口，并将数据从其输入端口路由到其数据发送端口，而其余工作通道设备在正常运行模式。

3. 发明授权

US06744293B1 Global clock tree de-skew 有权
标题翻译：全局时钟树去偏移
公开(公告)号：US06744293B1
公开(公告)日：2004-06-01
申请号：US10120576
申请日：2002-04-09
申请人： Wei Fu , Joseph J. Balardeta
发明人： Wei Fu , Joseph J. Balardeta
IPC分类号： H03L706
CPC分类号： G06F1/10 , H03L7/0814 , H03L7/089
摘要： A circuit and method for de-skewing a global clock tree is disclosed. A circuit uses a digital delay lock loop having an incoming clock input, a local reference clock input, and a clock output providing an output clock signal. The delay lock loop receives an incoming clock signal and aligns it with a local reference clock signal, where the incoming clock signal is a skewed version of the local reference clock signal. The circuit further includes a clock tree for receiving the output clock signal and outputting a global clock signal when the delay lock loop is in lock mode. The output clock signal of the global clock tree represents a phase lock between an incoming clock signal on the incoming clock input and a local reference clock signal input on the local reference clock input.
摘要翻译：公开了一种用于去偏斜全局时钟树的电路和方法。电路使用具有输入时钟输入，本地参考时钟输入和提供输出时钟信号的时钟输出的数字延迟锁定环路。延迟锁定环接收输入时钟信号并将其与本地参考时钟信号对齐，其中输入时钟信号是本地参考时钟信号的偏移版本。电路还包括时钟树，用于在延迟锁定环处于锁定模式时接收输出时钟信号并输出全局时钟信号。全局时钟树的输出时钟信号表示输入时钟输入端的输入时钟信号与本地参考时钟输入端输入的本地参考时钟信号之间的相位锁定。

4. 发明授权

US06642781B1 Selectable equalization system and method 有权
公开(公告)号：US06642781B1
公开(公告)日：2003-11-04
申请号：US10236761
申请日：2002-09-06
申请人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
发明人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
IPC分类号： H03B100
CPC分类号： H03H21/0001
摘要： A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

5. 发明授权

US06566967B1 Configurable triple phase-locked loop circuit and method 有权
标题翻译：可配置三相锁相环电路及方法
公开(公告)号：US06566967B1
公开(公告)日：2003-05-20
申请号：US10085458
申请日：2002-02-26
申请人： Sudhaker Reddy Anumula , Joseph J. Balardeta , Wei Fu , Paul Vanderbilt , Mehmet Mustafa Eker
发明人： Sudhaker Reddy Anumula , Joseph J. Balardeta , Wei Fu , Paul Vanderbilt , Mehmet Mustafa Eker
IPC分类号： H03L700
CPC分类号： H03L7/18 , H03L7/087 , H03L7/0891 , H03L7/107 , H03L7/113 , H03L7/14
摘要： A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.
摘要翻译：具有多个检测元件的可配置PLL架构。可配置PLL电路包括用于提供第一差分信号的第一检测器，用于提供第二差分信号的第二检测器，用于提供第三差分信号的第三检测器，以及用于使第一，第二和第第三检测器。 PLL电路还包括多路复用器，用于从相应的使能检测器接收至少一个差分信号，并提供多路复用的差分信号输出。在操作中，选择操作模式，并且启用一个或多个检测器以使用一个或多个输入参考信号进行操作。使能的检测器的输出由多路复用器接收以完成所选择的操作模式的操作。

6. 发明授权

US07139348B1 Distributed clock network using all-digital master-slave delay lock loops 有权
标题翻译：分布式时钟网络使用全数字主从延迟锁定环
公开(公告)号：US07139348B1
公开(公告)日：2006-11-21
申请号：US10120598
申请日：2002-04-09
申请人： Wei Fu , Joseph J. Balardeta
发明人： Wei Fu , Joseph J. Balardeta
IPC分类号： H03D3/24 , H03L7/06 , G06F1/12
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H03L2207/50 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L7/033
摘要： A distributed clock circuit for clocking high speed data at various different physical locations on a chip while improving setup and hold times. The clock circuit includes a master delay lock loop (DLL) circuit configured to lock a global clock signal with a first data signal, and output a clock delay control signal when the global clock signal is locked. The clock circuit further includes one or more slave DLL circuits, coupled to receive the clock delay control signal to lock a local clock signal with a local data signal, wherein the local clock signal is based on the global clock signal.
摘要翻译：一种分布式时钟电路，用于在提高设置和保持时间的同时在芯片上的各种不同物理位置对高速数据进行计时。时钟电路包括被配置为利用第一数据信号锁定全局时钟信号的主延迟锁定环（DLL）电路，并且当全局时钟信号被锁定时输出时钟延迟控制信号。时钟电路还包括一个或多个从属DLL电路，被耦合以接收时钟延迟控制信号以用本地数据信号锁定本地时钟信号，其中本地时钟信号基于全局时钟信号。

7. 发明授权

US07057418B1 High speed linear half-rate phase detector 有权
标题翻译：高速线性半速相位检测器
公开(公告)号：US07057418B1
公开(公告)日：2006-06-06
申请号：US10823060
申请日：2004-04-13
申请人： Wei Fu , Sudhaker Reddy Anumula , Hongwen Lu , Joseph J. Balardeta
发明人： Wei Fu , Sudhaker Reddy Anumula , Hongwen Lu , Joseph J. Balardeta
IPC分类号： G01R25/00
CPC分类号： H03D13/003 , G01R25/005
摘要： A high-speed, half rate phase detector provides an effective solution to the problem of XOR gate response to the minimum width signal precursors (Q1 and Q2) of a phase signal that indicates a phase difference between a data signal and a clock signal by combining the precursor signals in a multiplexer and combining the multiplexed signal with the data signal in an XOR gate. This affords the transition information in the transitions of the precursor signals, which is significant of phase difference, without requiring the XOR gate to respond to the minimum widths of those pulses.
摘要翻译：高速，半速率相位检测器提供了对相位信号的最小宽度信号前导（Q 1和Q 2）的异或门响应的问题的有效解决方案，该相位信号表示数据信号和时钟信号之间的相位差通过组合多路复用器中的前驱信号并将复用的信号与数据信号组合在异或门中。这提供了前驱信号的转变中的转换信息，其相位差是显着的，而不需要XOR门对这些脉冲的最小宽度做出响应。

8. 发明授权

US06545524B1 Configurable multiplexing circuit and method 有权
标题翻译：可配置复用电路和方法
公开(公告)号：US06545524B1
公开(公告)日：2003-04-08
申请号：US10085613
申请日：2002-02-26
申请人： Sudhaker Reddy Anumula , Wei Fu , Joseph J. Balardeta , Paul Vanderbilt , Allen C. Merrill
发明人： Sudhaker Reddy Anumula , Wei Fu , Joseph J. Balardeta , Paul Vanderbilt , Allen C. Merrill
IPC分类号： H03K1762
CPC分类号： H03L7/087 , H03L7/0891
摘要： A configurable multiplexing circuit and arrangement suited for phase locked loop applications. The multiplexing circuit includes an EX-OR element, a multiplexer element and a summer element. Each element is configured for receiving a particular type of detection signal output, as an input for one of multiple selectable multiplexing operations. The multiplexing circuit further includes a selection signal input, coupled to the EX-OR element, the multiplexer element and the summer element, for receiving a selection signal that enables one or more of the EX-OR element, the multiplexer element, and the summer element. Non-enabled elements are powered down to eliminate jitter and performance penalties.
摘要翻译：适用于锁相环应用的可配置复用电路和布置。复用电路包括EX-OR元件，复用器元件和加法元件。每个元件被配置为接收特定类型的检测信号输出，作为多个可选复用操作之一的输入。复用电路还包括耦合到EX-OR元件的选择信号输入，多路复用器元件和加法元件，用于接收使EX-OR元件，多路复用器元件和夏天中的一个或多个的选择信号元件。未使能的元件掉电，以消除抖动和性能损失。

9. 发明授权

US06502231B1 Integrated circuit template cell system and method 有权
标题翻译：集成电路模板单元系统及方法
公开(公告)号：US06502231B1
公开(公告)日：2002-12-31
申请号：US09871473
申请日：2001-05-31
申请人： Simon S. Pang , Rimon Shookhtim , Joseph J. Balardeta , Gary Wong
发明人： Simon S. Pang , Rimon Shookhtim , Joseph J. Balardeta , Gary Wong
IPC分类号： G06F1750
CPC分类号： H01L27/0292 , G06F17/5077 , H01L23/50 , H01L27/0251 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.
摘要翻译：提供了一种用于在集成电路（IC）的输入/输出（I / O）表面上形成模板单元的系统和方法。电池的第一金属层包括从电池的一个边缘延伸到另一边缘的多条平行的总线。第二底层金属层包括沿与第一层线垂直的方向延伸的总线线。信号路由层位于第二金属层下面，路由通道位于单元的边缘周围，并且ESD和输出缓冲电路放置在路由通道内。第一和第二金属层的总线以及信号路由层的路由信道具有连接区域，从而通过邻接单元形成连接。每个单元还包括覆盖在第一金属层上的倒装芯片焊盘，该焊盘可以通过通孔连接到第一或第二金属层。

10. 发明授权

US06469574B1 Selectable equalization system and method 有权
标题翻译：可选均衡系统和方法
公开(公告)号：US06469574B1
公开(公告)日：2002-10-22
申请号：US09771241
申请日：2001-01-26
申请人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
发明人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
IPC分类号： H03B100
CPC分类号： H03H21/0001
摘要： A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.
摘要翻译：已经提供了一种用于可选择地将输入信号均衡到集成电路（IC）的系统和方法，以补偿传输过程中的劣化。可选择均衡电路包括并行均衡和非均衡部分。当均衡部分被接合时，谐振元件修改电路阻抗以向电路传递函数添加零。当非均衡功能被接合时，均衡部分脱离而不降低栅极电容，并且输入信号在传递函数中被处理而没有零。

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