专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06876263B1 Dual voltage-controlled oscillator structure with powder-down feature 有权
标题翻译：双压控振荡器结构，具有粉碎功能
公开(公告)号：US06876263B1
公开(公告)日：2005-04-05
申请号：US10382638
申请日：2003-03-05
申请人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
发明人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
IPC分类号： H03B1/00 , H03B27/00
CPC分类号： H03B5/06 , H03B2200/0048
摘要： A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.
摘要翻译：压控振荡器（“VCO”）结构包括多个VCO电路，每个VCO电路具有不同的额定工作频率范围。通过各个VCO电路的选择性激活/去激活来调节VCO结构的功耗。在优选实施例中，在任何给定时间只有一个VCO电路是有效的。可以选择有源VCO以满足特定应用的要求和/或补偿半导体制造工艺变化。

2. 发明授权

US06720818B1 Method and apparatus for maximizing an amplitude of an output signal of a differential multiplexer 失效
标题翻译：用于最大化差分多路复用器的输出信号的幅度的方法和装置
公开(公告)号：US06720818B1
公开(公告)日：2004-04-13
申请号：US10290659
申请日：2002-11-08
申请人： Zhixiang Jason Liu , Shuyu Lei , Harry Huy Dang , Thomas Clark Bryan
发明人： Zhixiang Jason Liu , Shuyu Lei , Harry Huy Dang , Thomas Clark Bryan
IPC分类号： H03K1762
CPC分类号： H03K17/693 , H03K17/005 , H03K2217/0036
摘要： An amplitude of a differential output signal at a differential multiplexer is maximized by presenting, in response to a differential selection signal, a high impedance to each output port of each differential transistor of a non-selected differential transistor pair. A differential input signal is received at each differential transistor pair. Each transistor of each differential transistor pair is connected to a current source through an independent selection transistor. In response to the differential selection signal, each of the selection transistors is placed in an off state resulting in a high impedance between the output ports of the transistors of the non-selected differential transistor pair.
摘要翻译：通过响应于差分选择信号，向未选择的差分晶体管对的每个差分晶体管的每个输出端口呈现高阻抗，使差分多路复用器的差分输出信号的幅度最大化。在每个差分晶体管对接收差分输入信号。每个差分晶体管对的每个晶体管通过独立的选择晶体管连接到电流源。响应于差分选择信号，每个选择晶体管被置于截止状态，从而在未选择的差分晶体管对的晶体管的输出端口之间产生高阻抗。

3. 发明授权

US06552582B1 Source follower for low voltage differential signaling 有权
标题翻译：源极跟随器用于低电压差分信号
公开(公告)号：US06552582B1
公开(公告)日：2003-04-22
申请号：US09966388
申请日：2001-09-27
申请人： Thomas Clark Bryan , Harry Huy Dang
发明人： Thomas Clark Bryan , Harry Huy Dang
IPC分类号： H03B100
CPC分类号： H03K19/018514 , H03K17/6871 , H04L25/0272
摘要： A source follower circuit for low voltage differential signaling (LVDS) has a low power consumption, low noise, and the ability to drive a highly capacitive load at an output port of an integrated circuit (IC). The source follower circuit includes a first p-channel transistor having a drain coupled to a supply voltage and a gate coupled to a first input; a second p-channel transistor having a drain coupled to the supply voltage and a gate coupled to a second input which is complementary to the first input; a third p-channel transistor having a gate coupled to the second input, a source coupled to ground, and a drain coupled to a source of the first p-channel transistor which forms a first output; and a fourth p-channel transistor having a source coupled to the ground and a drain coupled to a source of the second p-channel transistor which forms a second output which is complementary to the first output. Advantageously, the output signals of the circuit are referenced to ground and are less affected by power supply variations.
摘要翻译：用于低电压差分信号（LVDS）的源极跟随器电路具有低功耗，低噪声以及在集成电路（IC）的输出端口处驱动高容性负载的能力。源极跟随器电路包括具有耦合到电源电压的漏极和耦合到第一输入的栅极的第一p沟道晶体管; 具有耦合到所述电源电压的漏极的第二p沟道晶体管和耦合到与所述第一输入互补的第二输入的栅极; 第三p沟道晶体管，其具有耦合到第二输入的栅极，耦合到地的源极和耦合到形成第一输出的第一p沟道晶体管的源极的漏极; 以及第四p沟道晶体管，其具有耦合到地的源极和耦合到第二p沟道晶体管的源极的漏极，其形成与第一输出互补的第二输出。有利地，电路的输出信号参考地，并且受电源变化的影响较小。

4. 发明授权

US06169421A Complementary metal-oxide semiconductor buffer 有权
标题翻译：互补金属氧化物半导体缓冲液
公开(公告)号：US06169421A
公开(公告)日：2001-01-02
申请号：US09303726
申请日：1999-05-03
申请人： Thomas Clark Bryan , Harry Huy Dang
发明人： Thomas Clark Bryan , Harry Huy Dang
IPC分类号： H03K190948
CPC分类号： H03K19/0013
摘要： A CMOS buffer for interfacing TTL-standard signals and capable of driving a high capacitance load such as a transmission line with low switching noise and low power consumption. The CMOS buffer includes two CMOS branch circuits that control the operation of a CMOS output device. Each branch circuit includes a first delay and a second delay greater than the first delay. The CMOS output device includes a complementary pair of MOS transistors. The first MOS transistor of the CMOS output device is operated by the first branch circuit in response to a signal that is delayed by the first or the second delay. The second MOS transistor of the CMOS output device is operated by the second branch circuit in response to delay of the signal by the second or the first delay.
摘要翻译：用于连接TTL标准信号并能够驱动高电容负载的CMOS缓冲器，例如具有低开关噪声和低功耗的传输线。 CMOS缓冲器包括两个CMOS分支电路，用于控制CMOS输出设备的工作。每个分支电路包括大于第一延迟的第一延迟和第二延迟。 CMOS输出装置包括一对互补的MOS晶体管。 CMOS输出装置的第一MOS晶体管响应于延迟了第一或第二延迟的信号由第一分支电路操作。 CMOS输出装置的第二MOS晶体管响应于第二或第一延迟的信号延迟由第二分支电路操作。

5. 发明授权

US5955924A Differential metal-oxide semiconductor (CMOS) push-pull buffer 失效
标题翻译：差分金属氧化物半导体（MOS）推挽式缓冲器
公开(公告)号：US5955924A
公开(公告)日：1999-09-21
申请号：US63528
申请日：1998-04-21
申请人： Thomas Clark Bryan , Harry Huy Dang
发明人： Thomas Clark Bryan , Harry Huy Dang
IPC分类号： H03F3/18 , H03F3/45 , H03F3/26
CPC分类号： H03F3/45076
摘要： A differential cMOS push-pull buffer includes a pair of push-pull sections, a cMOS current source transistor connected to the push-pull sections for providing current thereto, and two cMOS trickle current transistors, each connected to an output node of a respective push-pull section for conducting a trickle current at the output node. In each push-pull section a trickle current enhances the speed of operation, thereby maintaining desirable attributes in output waveforms.
摘要翻译：差分cMOS推挽缓冲器包括一对推挽部分，连接到用于提供电流的推挽部分的cMOS电流源晶体管和两个cMOS涓流电流晶体管，每个连接到相应推挽的输出节点 - 用于在输出节点处进行涓流电流的 - 空间部分。在每个推挽部分中，涓流电流增加了操作速度，从而在输出波形中保持期望的属性。

6. 发明授权

US06911871B1 Circuit with voltage clamping for bias transistor to allow power supply over-voltage 有权
标题翻译：具有用于偏置晶体管的钳位电路以允许电源过压的电路
公开(公告)号：US06911871B1
公开(公告)日：2005-06-28
申请号：US10387014
申请日：2003-03-11
申请人： Wei Li , Thomas Clark Bryan , Zhixiang Jason Liu
发明人： Wei Li , Thomas Clark Bryan , Zhixiang Jason Liu
IPC分类号： H03B27/00 , H03K3/03 , H03K17/0814
CPC分类号： H03K17/08142 , H03K3/0322
摘要： A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (VDD) that would otherwise exceed the reliability breakdown voltage limit of the bias current transistors.
摘要翻译：环形振荡器级包括两个差分晶体管对，其被配置为向差分输入信号增加可调整量的延迟。每个差分对由偏置电流晶体管偏置; 偏置电流晶体管被限制偏置电流晶体管的漏极电压的钳位晶体管“保护”。电压钳位晶体管能够使用否则将超过偏置电流晶体管的可靠性击穿电压极限的电源电压（V SUB DD）。

7. 发明授权

US06794918B1 Loop-back clock phase generator 有权
标题翻译：环回时钟相位发生器
公开(公告)号：US06794918B1
公开(公告)日：2004-09-21
申请号：US10402022
申请日：2003-03-27
申请人： Hongwen Lu , Thomas Clark Bryan
发明人： Hongwen Lu , Thomas Clark Bryan
IPC分类号： H03H1126
CPC分类号： G06F1/06 , H03K3/0322 , H03K5/133 , H03L7/083 , H03L7/0995 , H03L7/24
摘要： A clock generator circuit includes a plurality of phase delay elements connected in series. The phase delay elements provide delayed output clock signals relative to an input clock signal. The circuit employs a loop-back path that connects the output of the final phase delay element to the input of the first phase delay element. The loop-back path enables the circuit to maintain an accurate overall phase delay between the input clock signal and the output clock signal generated by the final phase delay element. When implemented to support differential clock signals, the inverted outputs of the phase delay elements also serve as delayed clock signals. In accordance with one practical embodiment, the clock phase generator circuit provides evenly distributed clock phases over one clock period.
摘要翻译：时钟发生器电路包括串联连接的多个相位延迟元件。相位延迟元件相对于输入时钟信号提供延迟的输出时钟信号。电路采用将最终相位延迟元件的输出连接到第一相位延迟元件的输入端的环回路径。环回路径使得电路能够在输入时钟信号和由最终相位延迟元件产生的输出时钟信号之间保持精确的整体相位延迟。当实现以支持差分时钟信号时，相位延迟元件的反相输出也用作延迟的时钟信号。根据一个实际实施例，时钟相位发生器电路在一个时钟周期内提供均匀分布的时钟相位。

8. 发明授权

US06664853B1 Wide-bandwidth differential signal amplifier 有权
标题翻译：宽带差分信号放大器
公开(公告)号：US06664853B1
公开(公告)日：2003-12-16
申请号：US10061735
申请日：2002-01-31
申请人： Runhua Sun , Thomas Clark Bryan , Zhixiang Jason Liu
发明人： Runhua Sun , Thomas Clark Bryan , Zhixiang Jason Liu
IPC分类号： H03F345
CPC分类号： H03F3/45197 , H03F2203/45458 , H03F2203/45496 , H03F2203/45631 , H03F2203/45702
摘要： An impedance element connecting the outputs of two transistors of a wide-bandwidth amplifier forms a zero. The output of transistor is connected to a current source. The wide-bandwidth amplifier has a bandwidth greater than conventional amplifiers utilizing a single current source without an increase in power dissipation.
摘要翻译：连接宽带宽放大器的两个晶体管的输出的阻抗元件形成零。晶体管的输出端连接到电流源。宽带宽放大器的带宽大于传统放大器，而不会增加功耗。

9. 发明授权

US6014062A Control circuit for a complementary metal-oxide semiconductor voltage controlled oscillator 失效
标题翻译：互补金属氧化物半导体压控振荡器的控制电路
公开(公告)号：US6014062A
公开(公告)日：2000-01-11
申请号：US63527
申请日：1998-04-21
申请人： Thomas Clark Bryan , Allen Carl Merrill
发明人： Thomas Clark Bryan , Allen Carl Merrill
IPC分类号： H03K3/0231 , H03K3/354 , H03B5/02
CPC分类号： H03K3/354 , H03K3/0231
摘要： An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. The control circuit provides the differential control voltage. The control circuit includes a first section for generating a control current and a pair of current mirror sections that divide the control current, generating a pair of differential control signal components as VGS potentials of a pair of CMOS transistors configured as current mirrors.
摘要翻译：集成电路互补金属氧化物硅（CMOS）压控振荡器（VCO）包括以环形配置连接的多个可变延迟元件，每个可变延迟元件包括一对并联的差分CMOS部分。每个可变延迟元件的并联连接的差分CMOS部分由差分控制电压控制，差动控制电压的幅度设定每个可变延迟元件的两个差分部分的相对工作电平。这些相对操作电平决定了通过可变延迟元件的延迟。控制电路提供差动控制电压。控制电路包括用于产生控制电流的第一部分和分配控制电流的一对电流镜部分，产生一对差分控制信号分量作为配置为电流镜的一对CMOS晶体管的VGS电位。

10. 发明授权

US6121804A High frequency CMOS clock recovery circuit 有权
标题翻译：高频CMOS时钟恢复电路
公开(公告)号：US6121804A
公开(公告)日：2000-09-19
申请号：US140840
申请日：1998-08-27
申请人： Thomas Clark Bryan , Allen Carl Merrill , Wei Fu
发明人： Thomas Clark Bryan , Allen Carl Merrill , Wei Fu
IPC分类号： H03D13/00 , H03L7/089 , H04L7/033 , H03L7/00
CPC分类号： H04L7/033 , H03D13/003 , H03L7/089
摘要： A complementary metal-oxide semiconductor (CMOS) integrated circuit that includes a clock recovery circuit. The clock recovery circuit automatically properly aligns a clock with data. A latch is used to perform the function of a flip-flop. Because the flip flop is essentially two latches, using the latch rather than the flip flop results in a circuit having one less latch. Consequently, the circuit has less propagation delay, which permits higher frequency operation. Use of the latch also reduces the load on the clock and saves power. Additionally, the clock recovery circuit uses differential logic, which decreases noise sensitivity and allows higher frequency operation.
摘要翻译：一种互补金属氧化物半导体（CMOS）集成电路，其包括时钟恢复电路。时钟恢复电路自动将时钟与数据正确对齐。锁存器用于执行触发器的功能。因为触发器本质上是两个锁存器，所以使用锁存器而不是触发器导致具有少一个锁存器的电路。因此，电路具有较少的传播延迟，这允许更高频率的操作。使用锁存器还可以减少时钟上的负载并节省电力。此外，时钟恢复电路使用差分逻辑，这降低了噪声灵敏度，并允许更高频率的操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式