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1. 发明授权

US08629501B2 Stress-generating structure for semiconductor-on-insulator devices 有权
标题翻译：绝缘体上半导体器件的应力产生结构
公开(公告)号：US08629501B2
公开(公告)日：2014-01-14
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

2. 发明申请

US20100330763A1 METHOD OF CREATING ASYMMETRIC FIELD-EFFECT-TRANSISTORS 有权
标题翻译：创建不对称场效应晶体管的方法
公开(公告)号：US20100330763A1
公开(公告)日：2010-12-30
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对与基底垂直。

3. 发明申请

US20100006926A1 METHODS FOR FORMING HIGH PERFORMANCE GATES AND STRUCTURES THEREOF 失效
标题翻译：形成高性能门和其结构的方法
公开(公告)号：US20100006926A1
公开(公告)日：2010-01-14
申请号：US12170687
申请日：2008-07-10
申请人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

4. 发明授权

US07611954B2 Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same 失效
标题翻译：双极晶体管自对准具有凸起的外在基极延伸及其形成方法
公开(公告)号：US07611954B2
公开(公告)日：2009-11-03
申请号：US11150894
申请日：2005-06-13
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
IPC分类号： H01L21/8222
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.
摘要翻译：公开了具有包括外部区域和不同掺杂浓度的内部区域的升高的外部基极的自对准双极晶体管结构和制造晶体管的方法。更具体地说，外部碱基与发射体的自对准是通过在两个区域中形成外部碱基来实现的。首先，提供具有第一掺杂浓度的硅或多晶硅的第一材料以形成外部外在基极区域。然后通过光刻形成在第一材料层中的第一开口，在该第一材料层内形成有虚拟发射极基座，这导致在第一开口的侧壁和虚拟基座之间形成沟槽。然后在沟槽的内部提供第二掺杂浓度的第二材料，形成不同的内部非本征基本延伸区域，以将凸起的本征基底边缘自对准到虚拟基座边缘。由于发射极形成在存在虚拟基座的位置，所以外部基极也与发射极自对准。形成内部非本征基极延伸区域的硅或多晶硅也可以在具有选择性或非选择性外延的沟槽中生长。

5. 发明授权

US07611953B2 Bipolar transistor with isolation and direct contacts 失效
标题翻译：双极晶体管具有隔离和直接接触
公开(公告)号：US07611953B2
公开(公告)日：2009-11-03
申请号：US11677776
申请日：2007-02-22
申请人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
发明人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.
摘要翻译：双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。消除了常规的通孔和掩埋层以及它们的相关电阻。晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。该结构提供了改进的电气性能，包括改进的fT，Fmax和驱动电流。

6. 发明授权

US06960820B2 Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same 有权
标题翻译：双极晶体管自对准具有凸起的外在基极延伸及其形成方法
公开(公告)号：US06960820B2
公开(公告)日：2005-11-01
申请号：US10604212
申请日：2003-07-01
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
IPC分类号： H01L29/737 , H01L21/331 , H01L21/8222 , H01L29/10 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.
摘要翻译：公开了具有包括外部区域和不同掺杂浓度的内部区域的升高的外部基极的自对准双极晶体管结构和制造晶体管的方法。更具体地说，外部碱基与发射体的自对准是通过在两个区域中形成外部碱基来实现的。首先，提供具有第一掺杂浓度的硅或多晶硅的第一材料以形成外部外在基极区域。然后通过光刻形成在第一材料层中的第一开口，在该第一材料层内形成有虚拟发射极基座，这导致在第一开口的侧壁和虚拟基座之间形成沟槽。然后在沟槽内部设置第二掺杂浓度的第二材料，形成不同的内部非本征基本延伸区域，以将凸起的本征基底边缘自对准到虚拟基座边缘。由于发射极形成在存在虚拟基座的位置，所以外部基极也与发射极自对准。形成内部非本征基极延伸区域的硅或多晶硅也可以在具有选择性或非选择性外延的沟槽中生长。

7. 发明授权

US06864517B2 Bipolar structure with two base-emitter junctions in the same circuit 失效
标题翻译：在同一电路中具有两个基极 - 发射极结的双极结构
公开(公告)号：US06864517B2
公开(公告)日：2005-03-08
申请号：US10342424
申请日：2003-01-14
申请人： Gregory G. Freeman
发明人： Gregory G. Freeman
IPC分类号： H01L21/331 , H01L21/8228 , H01L29/10 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/66242 , H01L21/82285 , H01L29/1004 , H01L29/7378
摘要： Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has a lower ramp rate.
摘要翻译：采用SiGe技术的双极集成电路结合了提供掩模选择型双极晶体管。高性能/高可变性类型具有薄的基极，其中来自发射极的扩散与基极集电极结附近的Ge浓度的“斜坡”内的基极掺杂剂扩散相交，并且较低的性能/较低变异性类型具有额外的外延使得发射极扩散与Ge斜坡相交，其中斜坡具有较低的斜率。

8. 发明授权

US06531720B2 Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors 有权
公开(公告)号：US06531720B2
公开(公告)日：2003-03-11
申请号：US09838417
申请日：2001-04-19
申请人： Gregory G. Freeman , David R. Greenberg , Shwu-Jen Jeng
发明人： Gregory G. Freeman , David R. Greenberg , Shwu-Jen Jeng
IPC分类号： H01L2976
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： A method for forming a heterojunction bipolar transistor includes forming two sets of spacers on the sides of an emitter pedestal. After the first set of spacers is formed, first extrinsic base regions are implanted on either side of an intrinsic base. The second set of spacers is formed on the first set of spacers. Second extrinsic base regions are then implanted on respective sides of the intrinsic base. By using two sets of spacers, the first and second extrinsic base regions have different widths. This advantageously brings the combined extrinsic base structure closer to the emitter of the transistor but not closer to the collector. As a result, the base parasitic resistance is reduced along with collector-to-extrinsic base parasitic capacitance. The performance of the transistor is further enhanced as a result of the extrinsic base regions being self-aligned to the emitter and collector.

9. 发明授权

US08232603B2 Gated diode structure and method including relaxed liner 有权
标题翻译：门极二极管结构及方法包括松弛衬垫
公开(公告)号：US08232603B2
公开(公告)日：2012-07-31
申请号：US12702380
申请日：2010-02-09
申请人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
发明人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
IPC分类号： H01L21/70
CPC分类号： H01L21/28518 , H01L21/76829 , H01L29/66356 , H01L29/7391
摘要： A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
摘要翻译：门控二极管结构和用于制造门控二极管结构的方法使用从应力衬里导出的松弛衬垫，其通常用于与栅极二极管结构同时形成的场效应晶体管的上下文中。复杂的衬垫与应力衬里的处理（例如离子注入处理）形成。与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。

10. 发明授权

US07863143B2 High performance schottky-barrier-source asymmetric MOSFETs 有权
标题翻译：高性能肖特基势垒源非对称MOSFET
公开(公告)号：US07863143B2
公开(公告)日：2011-01-04
申请号：US12113462
申请日：2008-05-01
申请人： Qingqing Liang , Huilong Zhu , Gregory G. Freeman
发明人： Qingqing Liang , Huilong Zhu , Gregory G. Freeman
IPC分类号： H01L21/336
CPC分类号： H01L29/7839 , H01L29/41766 , H01L29/456 , H01L29/458 , H01L29/47 , H01L29/4933 , H01L29/665 , H01L29/66772 , H01L29/78618 , H01L29/78624
摘要： The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the drain dopant region. The semiconducting device may further include a gate structure overlying the channel of the semiconducting body. Further, a drain contact may be present to the drain dopant region of the semiconducting body, the drain contact being composed of a conductive material and in direct physical contact with a portion of a sidewall of the semiconducting body having a dimension that is less than a thickness of the semiconducting body in which the drain dopant region is positioned.
摘要翻译：在一个实施例中，本发明提供一种半导体器件，其包括半导体本体的第一端包括肖特基势垒区的半导体器件，半导体本体的第二端处的漏极掺杂区域和位于肖特基势垒区域和漏极掺杂剂区域。半导体器件还可以包括覆盖半导体本体的沟道的栅极结构。此外，漏极接触可以存在于半导体本体的漏极掺杂区域，漏极接触由导电材料构成，并且与半导体本体的侧壁的一部分直接物理接触，其尺寸小于其中漏极掺杂剂区域位于其中的半导体的厚度。

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