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1. 发明授权

US09991370B2 Methods and systems for ultra-high quality gated hybrid devices and sensors 有权
公开(公告)号：US09991370B2
公开(公告)日：2018-06-05
申请号：US14963364
申请日：2015-12-09
申请人： THE ROYAL INSTITUTION FOR THE ADVANCMENT OF LEARNING/MCGILL UNIVERSITY
发明人： Guillaume Gervais , Keyan Bennaceur
IPC分类号： H01L29/76 , H01L29/66 , H01L29/82 , H01L29/205 , H01L29/778 , H01L29/10 , H01L29/772
CPC分类号： H01L29/7606 , H01L29/1025 , H01L29/205 , H01L29/66977 , H01L29/7727 , H01L29/778 , H01L29/82
摘要： High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2DEG. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2DEG quality which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage. By exploiting a flip-chip methodology such damaging processing steps are separated to a second die/wafer which is then coupled to the 2DEG wafer. Extensions of the technique with two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and “zero” DEG structures.

2. 发明申请

US20170278961A1 SEMICONDUCTOR DEVICES WITH AN ENHANCED RESISTIVITY REGION AND METHODS OF FABRICATION THEREFOR 审中-公开
公开(公告)号：US20170278961A1
公开(公告)日：2017-09-28
申请号：US15083084
申请日：2016-03-28
申请人： Freescale Semiconductor, Inc.
发明人： Darrell Hill , Bruce Green
IPC分类号： H01L29/778 , H01L29/205 , H01L29/66 , H01L29/10 , H01L21/02 , H01L21/265 , H01L29/20 , H01L29/207
CPC分类号： H01L29/7787 , H01L21/02458 , H01L21/0254 , H01L21/26546 , H01L29/1025 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/32 , H01L29/66462 , H01L29/7786
摘要： Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer, and an enhanced resistivity region with an upper boundary proximate to an upper surface of the first semiconductor layer. The enhanced resistivity region has an upper boundary located a distance below the channel. Embodiments of a method of fabricating the semiconductor device include implanting one or more ion species through the first semiconductor layer to form the enhanced resistivity region.

3. 发明授权

US09748368B2 Tunnel field-effect transistor (TFET) with supersteep sub-threshold swing 有权
公开(公告)号：US09748368B2
公开(公告)日：2017-08-29
申请号：US14902480
申请日：2013-08-23
申请人： University of Calcutta
发明人： Abhijit Mallik
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/786
CPC分类号： H01L29/66977 , H01L29/0657 , H01L29/0843 , H01L29/1025 , H01L29/66356 , H01L29/66742 , H01L29/7391 , H01L29/78618 , H01L29/78696
摘要： Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (VDD) operations. In some examples, the GoGeS structure may include an increase in tunneling area and, thereby, a corresponding increases in the ON-state current ION. In order to achieve supersteep sub-threshold swing, both the lateral tunneling due to gate electric-field and the non-uniform tunneling at the gate-edge due to field-induced barrier lowering (FIBL) may be suppressed through selection of component dimension in the device structure. Example devices may be fabricated using CMOS fabrication technologies with the addition of selective etching in the process flow.

4. 发明申请

US20170069738A1 TUNNELING FIELD EFFECT TRANSISTORS WITH A VARIABLE BANDGAP CHANNEL 有权
标题翻译：具有可变带宽通道的隧道场效应晶体管
公开(公告)号：US20170069738A1
公开(公告)日：2017-03-09
申请号：US15122402
申请日：2014-03-28
申请人： UYGAR E. AVCI , DMITRI E. NIKONOV , IAN A. YOUNG
发明人： UYGAR E. AVCI , DMITRI E. NIKONOV , IAN A. YOUNG
IPC分类号： H01L29/66 , H01L29/10 , H01L29/08 , H01L29/786 , H01L49/00 , H01L29/24 , H01L29/423
CPC分类号： H01L29/66977 , H01L25/16 , H01L29/0847 , H01L29/1025 , H01L29/1054 , H01L29/24 , H01L29/42384 , H01L29/42392 , H01L29/66356 , H01L29/66969 , H01L29/7391 , H01L29/78648 , H01L49/003
摘要： Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field. In some embodiments the variable bandgap channel may be configured to modulate from an ON to an OFF state and vice versa in response to the application and/or withdrawal of a force. The variable bandgap channel may exhibit a bandgap that is smaller in the ON state than in the OFF state. As a result, the TFETs may exhibit one or more of relatively high on current, relatively low off current, and sub-threshold swing below 60 mV/decade.
摘要翻译：描述包括可变带隙通道的隧穿场效应晶体管（TFET）。在一些实施例中，可变带隙通道的一个或多个带隙特性可以通过施加或取出诸如电压或电场的力中的至少一个来动态改变。在一些实施例中，可变带隙通道可以被配置成响应于施加和/或撤回力而从接通到关闭状态和反之亦然。可变带隙通道可以表现出在ON状态下比在OFF状态下更小的带隙。结果，TFET可以呈现出一个或多个相对较高的导通电流，相对低的关断电流以及低于60mV /十倍的次阈值摆幅。

5. 发明授权

US09431520B2 Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates 有权
公开(公告)号：US09431520B2
公开(公告)日：2016-08-30
申请号：US14810017
申请日：2015-07-27
申请人： GLOBALFOUNDRIES INC.
发明人： Guy M. Cohen , Christos D. Dimitrakopoulos , Alfred Grill
IPC分类号： H01L29/66 , H01L29/775 , H01L21/3105 , H01L21/306 , H01L21/02 , H01L21/324 , B82Y10/00 , B82Y40/00 , H01L29/06 , H01L29/10 , H01L29/16 , H01L51/00 , H01L21/28 , H01L29/78 , H01L51/05 , B82Y99/00
CPC分类号： H01L29/66795 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L21/02057 , H01L21/02381 , H01L21/02527 , H01L21/02529 , H01L21/02636 , H01L21/28008 , H01L21/30604 , H01L21/31051 , H01L21/324 , H01L29/0673 , H01L29/1025 , H01L29/1606 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L29/785 , H01L51/0045 , H01L51/0048 , H01L51/0558
摘要： Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

6. 发明申请

US20150171089A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150171089A1
公开(公告)日：2015-06-18
申请号：US14628724
申请日：2015-02-23
申请人： PS4 Luxco S.a.r.l.
发明人： Hiroaki TAKETANI
IPC分类号： H01L27/108 , H01L29/10 , H01L29/06 , H01L29/08 , H01L29/49 , H01L29/423
CPC分类号： H01L27/10823 , H01L21/76224 , H01L27/108 , H01L27/10814 , H01L27/10829 , H01L27/10876 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1025 , H01L29/1095 , H01L29/4236 , H01L29/4916 , H01L29/4966 , H01L29/7827
摘要： A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.
摘要翻译：包括半导体器件的半导体器件可以包括但不限于半导体衬底，隔离电极，栅极电极，栅极绝缘膜和第一绝缘膜。半导体衬底具有第一凹槽和第二凹槽。隔离电极位于第一槽中。栅电极位于第二槽中。栅极绝缘膜与栅电极相邻。第一绝缘膜与隔离电极相邻。隔离电极的阈值电压比栅电极大。

7. 发明申请

US20140054657A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140054657A1
公开(公告)日：2014-02-27
申请号：US13766566
申请日：2013-02-13
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Akira HOKAZONO , Yoshiyuki KONDO , Toshitaka MIYATA
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L29/0843 , H01L29/1025 , H01L29/66356 , H01L29/66477 , H01L29/7391
摘要： In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface of the substrate so as to sandwich the gate electrode. The device further includes a junction forming region disposed between the source diffusion layer and the drain diffusion layer so as to contact the source diffusion layer. The junction forming region includes a source extension layer of the first conductivity type, a pocket layer of the second conductivity type above the source extension layer, and a diffusion suppressing layer disposed between the source extension layer and the pocket layer and containing carbon so as to suppress diffusion of impurities between the source extension layer and the pocket layer.
摘要翻译：在一个实施例中，半导体器件包括衬底，衬底上的栅极绝缘体和栅极绝缘体上的栅电极。该器件还包括第一导电类型的源极扩散层和第二导电类型的漏极扩散层，设置在衬底的表面上以夹着栅电极。该器件还包括设置在源极扩散层和漏极扩散层之间以便与源极扩散层接触的结形成区域。结形成区域包括第一导电类型的源极延伸层，在源延伸层上方的第二导电类型的袋层，以及设置在源延伸层和袋层之间并且含有碳的扩散抑制层，以便抑制杂质在源延伸层和袋层之间的扩散。

8. 发明申请

US20140051217A1 GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES 有权
公开(公告)号：US20140051217A1
公开(公告)日：2014-02-20
申请号：US14064791
申请日：2013-10-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy M. Cohen , Christos D. Dimitrakopoulos , Alfred Grill
IPC分类号： H01L29/66 , H01L21/28
CPC分类号： H01L29/66795 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L21/02057 , H01L21/02381 , H01L21/02527 , H01L21/02529 , H01L21/02636 , H01L21/28008 , H01L21/30604 , H01L21/31051 , H01L21/324 , H01L29/0673 , H01L29/1025 , H01L29/1606 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L29/785 , H01L51/0045 , H01L51/0048 , H01L51/0558
摘要： Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

9. 发明申请

US20060255373A1 Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure 有权
标题翻译：包括高掺杂导电沟道区的半导体结构和用于制造半导体结构的方法
公开(公告)号：US20060255373A1
公开(公告)日：2006-11-16
申请号：US10549784
申请日：2003-03-19
申请人： Rudolf Elpelt , Heinz Mitlehner , Reinhold Schorner
发明人： Rudolf Elpelt , Heinz Mitlehner , Reinhold Schorner
IPC分类号： H01L29/80
CPC分类号： H01L29/1608 , H01L29/0634 , H01L29/1025 , H01L29/1029 , H01L29/1033 , H01L29/66053 , H01L29/66068 , H01L29/7392 , H01L29/7722 , H01L29/7828 , H01L29/8083 , H01L29/8122
摘要： The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (2), a current path that runs within the first semiconductor region (2) and a channel region (22). The channel region (22) forms part of the first semiconductor region (2) and comprises a base doping. The current (I) in the channel region (22) can be influenced by means of at least one depletion zone (23, 24). The channel region (22) contains an n-conductive channel region (225) for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region (225) is produced by ionic implantation in an epitaxial layer (262) that surrounds the channel region (22).
摘要翻译：本发明涉及一种用于控制电流（I）的半导体结构，包括第一n导电半导体区域（2），在第一半导体区域（2）内延伸的电流路径和沟道区域（22）。沟道区域（22）形成第一半导体区域（2）的一部分并且包括基极掺杂。通道区域（22）中的电流（I）可以通过至少一个耗尽区（23,24）的影响。沟道区（22）包含用于传导电流的n导电沟道区（225），所述后区具有比基底掺杂更高的掺杂水平。导电沟道区域（225）通过离子注入在围绕沟道区域（22）的外延层（262）中产生。

10. 发明授权

US09123695B2 Nanowire field-effect transistor and method for manufacturing same 有权
标题翻译：纳米线场效应晶体管及其制造方法
公开(公告)号：US09123695B2
公开(公告)日：2015-09-01
申请号：US14385450
申请日：2013-03-11
申请人： POSTECH ACADEMY—INDUSTRY FOUNDATION
发明人： ChangKi Baek , TaiUk Rim , MyungDong Ko
IPC分类号： H01L29/06 , H01L29/423 , H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66 , H01L29/10 , B82Y15/00
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y15/00 , B82Y40/00 , H01L29/0676 , H01L29/1025 , H01L29/66439 , H01L29/775 , Y10S977/891 , Y10S977/938
摘要： Provided are a nanowire field-effect transistor and a method for manufacturing the same. The nanowire field-effect transistor can enable a source region to be positioned, with respect to an asymmetrical nanowire channel, adjacent to a region in which the diameter of the nanowire channel is large, can enable a drain region to be positioned adjacent to a region in which the diameter of the nanowire channel is small, can enable an ON current to be increased in a state in which a threshold voltage level is kept the same, and can enable the current drivability of a gate electrode to be improved.
摘要翻译：提供一种纳米线场效应晶体管及其制造方法。纳米线场效应晶体管可以使得源区域相对于不对称的纳米线通道被定位，所述非对称纳米线通道与纳米线通道的直径大的区域相邻，可以使漏极区域邻近区域其中纳米线通道的直径小，能够使阈值电压水平保持相同的状态下的导通电流增加，能够提高栅电极的电流驱动能力。

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