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1. 发明授权

US09059316B2 Structure and method for mobility enhanced MOSFETs with unalloyed silicide 有权
标题翻译：具有非合金化硅化物的迁移率增强型MOSFET的结构和方法
公开(公告)号：US09059316B2
公开(公告)日：2015-06-16
申请号：US13397860
申请日：2012-02-16
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/78 , H01L27/32 , H01L29/165
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

2. 发明授权

US08871576B2 Silicon nanotube MOSFET 有权
标题翻译：硅纳米管MOSFET
公开(公告)号：US08871576B2
公开(公告)日：2014-10-28
申请号：US13036292
申请日：2011-02-28
申请人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
发明人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
IPC分类号： H01L29/49 , H01L29/06 , B82Y10/00 , H01L29/775 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , B82Y10/00 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer; forming an outer gate surrounding the cylindrical Si layer and positioned between a bottom spacer and a top spacer; growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.
摘要翻译：纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部和外部栅极，以及分别由围绕管状内部和外部门的间隔开的源极和漏极。形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层; 形成围绕圆柱形Si层并位于底部间隔件和顶部间隔件之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

3. 发明授权

US08803243B2 Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
标题翻译：具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件
公开(公告)号：US08803243B2
公开(公告)日：2014-08-12
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L21/70
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

4. 发明申请

US20130320340A1 CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS 有权
公开(公告)号：US20130320340A1
公开(公告)日：2013-12-05
申请号：US13488532
申请日：2012-06-05
申请人： Emrah Acar , Aditya Bansal , Dureseti Chidambarrao , Liang-Teck Pang , Amith Singhee
发明人： Emrah Acar , Aditya Bansal , Dureseti Chidambarrao , Liang-Teck Pang , Amith Singhee
IPC分类号： H01L21/66 , H01L23/50
CPC分类号： H01L22/34 , H01L22/14 , H01L27/0203 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

5. 发明授权

US08476706B1 CMOS having a SiC/SiGe alloy stack 有权
标题翻译：具有SiC / SiGe合金叠层的CMOS
公开(公告)号：US08476706B1
公开(公告)日：2013-07-02
申请号：US13343472
申请日：2012-01-04
申请人： Dureseti Chidambarrao , Brian J. Greene , Yue Liang , Xiaojun Yu
发明人： Dureseti Chidambarrao , Brian J. Greene , Yue Liang , Xiaojun Yu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66651
摘要： A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.
摘要翻译：通过在硅表面上沉积硅碳合金层，在硅表面上提供硅的δ掺杂，硅表面可以是体硅衬底的水平表面，绝缘体上半导体衬底的顶部硅层的水平表面，或硅片的垂直表面。可以通过在PFET区域中而不是在NFET区域中选择性地沉积硅锗合金层来区分p型场效应晶体管（PFET）区域和n型场效应晶体管（NFET）区域。 PFET区域中的硅锗合金层可以覆盖或叠加在硅碳合金层上。普通材料堆叠可用于PFET和NFET的栅极电介质和栅电极。 PFET和NFET的每个沟道包括硅碳合金层，并且通过硅锗层的存在或不存在来区分。

6. 发明授权

US08429576B2 Methods and system for analysis and management of parametric yield 有权
公开(公告)号：US08429576B2
公开(公告)日：2013-04-23
申请号：US13471789
申请日：2012-05-15
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F17/50
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

7. 发明授权

US08368125B2 Multiple orientation nanowires with gate stack stressors 失效
标题翻译：具有栅堆叠应力的多取向纳米线
公开(公告)号：US08368125B2
公开(公告)日：2013-02-05
申请号：US12505580
申请日：2009-07-20
申请人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
IPC分类号： H01L27/085
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译：电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加取决于通道长度相对于晶体结构的对准。给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

8. 发明授权

US08299622B2 IC having viabar interconnection and related method 有权
标题翻译： IC具有viabar互连及相关方法
公开(公告)号：US08299622B2
公开(公告)日：2012-10-30
申请号：US12186061
申请日：2008-08-05
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

9. 发明授权

US08296691B2 Methodology for improving device performance prediction from effects of active area corner rounding 失效
标题翻译：从活动区域四舍五入的角度提高设备性能预测的方法
公开(公告)号：US08296691B2
公开(公告)日：2012-10-23
申请号：US11971015
申请日：2008-01-08
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F17/50 , G06F9/45 , G06G7/48
CPC分类号： G06F17/5036
摘要： A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.
摘要翻译：一种用于建模半导体晶体管器件结构的系统和方法，所述半导体晶体管器件结构具有设计长度的导线特征，所述导线特征与待建模的电路中的晶体管器件的栅极连接，所述晶体管包括有源器件（RX）形成并且其上延伸有导线特征。该方法包括提供分析模型表示，其包括用于建模影响有源器件区域宽度的光刻火炬效应的功能; 并且从建模功能将有源器件区域宽度（deltaW加法器）的有效变化与距离RX区域的限定边缘的距离的函数相关联。然后，器件的晶体管紧凑型模型中的晶体管模型参数值被更新为包括要添加到内置deltaW值的ΔW加法器值。在模拟中使用的网表包括deltaW加法器值，以更精确地描述被建模的晶体管器件的特性，包括对晶体管器件参数的光刻拐角舍入效应的建模。

10. 发明申请

US20120261672A1 MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS 失效
标题翻译：通过使用电介质间隔来最小化CMOS晶体管的漏电流和结电容
公开(公告)号：US20120261672A1
公开(公告)日：2012-10-18
申请号：US13084594
申请日：2011-04-12
申请人： Dureseti Chidambarrao , Ramachandran Muralidhar , Philip J. Oldiges , Viorel Ontalus
发明人： Dureseti Chidambarrao , Ramachandran Muralidhar , Philip J. Oldiges , Viorel Ontalus
IPC分类号： H01L27/092 , H01L21/782 , H01L21/8238 , H01L27/12
CPC分类号： H01L21/823814 , H01L21/3086 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L21/84
摘要： A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.
摘要翻译：公开了用于形成用于互补金属氧化物半导体场效应晶体管（CMOS晶体管）的电介质间隔物和外延层的半导体结构和方法。具体地，该结构和方法包括形成设置在沟槽中并且与硅衬底相邻的电介质间隔物，这使漏电流最小化。此外，沉积外延层以形成源极和漏极区域，其中源极区域和漏极区域彼此间隔一定距离。外延层邻近电介质间隔物和晶体管本体区域（即，栅极下方的衬底部分）设置，这可使晶体管结电容最小化。最小化晶体管结电容可以提高CMOS晶体管的开关速度。因此，应用介电间隔物和外延层以最小化CMOS晶体管中的漏电流和晶体管结电容可以增强低功率应用中CMOS晶体管的效用和性能。

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