专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08232603B2 Gated diode structure and method including relaxed liner 有权
标题翻译：门极二极管结构及方法包括松弛衬垫
公开(公告)号：US08232603B2
公开(公告)日：2012-07-31
申请号：US12702380
申请日：2010-02-09
申请人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
发明人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
IPC分类号： H01L21/70
CPC分类号： H01L21/28518 , H01L21/76829 , H01L29/66356 , H01L29/7391
摘要： A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
摘要翻译：门控二极管结构和用于制造门控二极管结构的方法使用从应力衬里导出的松弛衬垫，其通常用于与栅极二极管结构同时形成的场效应晶体管的上下文中。复杂的衬垫与应力衬里的处理（例如离子注入处理）形成。与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。

2. 发明申请

US20100237421A1 Gated Diode Structure and Method Including Relaxed Liner 有权
标题翻译：封闭二极管结构和方法包括轻松衬里
公开(公告)号：US20100237421A1
公开(公告)日：2010-09-23
申请号：US12702380
申请日：2010-02-09
申请人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
发明人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
IPC分类号： H01L27/06 , H01L21/70
CPC分类号： H01L21/28518 , H01L21/76829 , H01L29/66356 , H01L29/7391
摘要： A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
摘要翻译：门控二极管结构和用于制造门控二极管结构的方法使用从应力衬里导出的松弛衬垫，其通常用于与栅极二极管结构同时形成的场效应晶体管的上下文中。复杂的衬垫与应力衬里的处理（例如离子注入处理）形成。与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。

3. 发明申请

US20130328124A1 GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
标题翻译：用于消除从盖拆卸中的RIE损伤的栅极二极管结构
公开(公告)号：US20130328124A1
公开(公告)日：2013-12-12
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06 , H01L21/8238
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

4. 发明申请

US20110163383A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20110163383A1
公开(公告)日：2011-07-07
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

5. 发明授权

US07804140B2 Field effect transistor with reduced shallow trench isolation induced leakage current 失效
标题翻译：场效应晶体管减少浅沟槽隔离引起的漏电流
公开(公告)号：US07804140B2
公开(公告)日：2010-09-28
申请号：US12041967
申请日：2008-03-04
申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L27/088
CPC分类号： H01L29/4238 , H01L29/7833
摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
摘要翻译：沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。

6. 发明授权

US08779551B2 Gated diode structure for eliminating RIE damage from cap removal 失效
标题翻译：门二极管结构，用于消除去除盖子的RIE损坏
公开(公告)号：US08779551B2
公开(公告)日：2014-07-15
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

7. 发明授权

US07956415B2 SOI transistor having a carrier recombination structure in a body 失效
标题翻译：在体内具有载流子复合结构的SOI晶体管
公开(公告)号：US07956415B2
公开(公告)日：2011-06-07
申请号：US12133686
申请日：2008-06-05
申请人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
发明人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78612
摘要： A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.
摘要翻译：顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

8. 发明申请

US20090315138A1 METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE 有权
标题翻译：具有降低PARASITIC电容的SOI体接触FET的方法和结构
公开(公告)号：US20090315138A1
公开(公告)日：2009-12-24
申请号：US12141276
申请日：2008-06-18
申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/3205
CPC分类号： H01L29/78615 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.
摘要翻译：在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。

9. 发明授权

US08232599B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08232599B2
公开(公告)日：2012-07-31
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

10. 发明申请

US20120187492A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20120187492A1
公开(公告)日：2012-07-26
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式