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1. 发明申请

US20110079851A1 SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS 有权
标题翻译： SOI MOSFET中高效地接地层分离层析
公开(公告)号：US20110079851A1
公开(公告)日：2011-04-07
申请号：US12574126
申请日：2009-10-06
申请人： YING LI , Shreesh Narasimha , Werner A. Rausch
发明人： YING LI , Shreesh Narasimha , Werner A. Rausch
IPC分类号： H01L29/06 , H01L29/772 , H01L21/762
CPC分类号： H01L29/78615 , H01L21/74 , H01L21/76229 , H01L21/76283 , H01L29/66772
摘要： Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.
摘要翻译：公开了一种体硅层上的SOI器件，其具有FET区，体接触区和STI区。 FET区域由SOI层和上覆栅极构成。 STI区域包括将SOI器件与相邻SOI器件分开的第一STI层。身体接触区域包括SOI层的延伸部，延伸部上的第二STI层和与延伸部接触的身体接触部。第一和第二STI层是连续的和不同的厚度，以便形成分级STI。

2. 发明授权

US07790541B2 Method and structure for forming multiple self-aligned gate stacks for logic devices 有权
标题翻译：用于形成用于逻辑器件的多个自对准栅极堆叠的方法和结构
公开(公告)号：US07790541B2
公开(公告)日：2010-09-07
申请号：US11950095
申请日：2007-12-04
申请人： Bruce B. Doris , Mahender Kumar , Werner A. Rausch , Robin Van Den Nieuwenhuizen
发明人： Bruce B. Doris , Mahender Kumar , Werner A. Rausch , Robin Van Den Nieuwenhuizen
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/76
CPC分类号： H01L21/823878 , H01L21/823842
摘要： A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.
摘要翻译：一种用于形成多个自对准栅极堆叠的方法，所述方法包括：在衬底的第一部分上形成第一组栅极堆叠层，在所述衬底的邻近所述第一部分的第二部分上形成第二组栅极堆叠层蚀刻以形成设置在衬底的第一部分和第二部分之间的沟槽，并用绝缘材料填充沟槽。

3. 发明申请

US20090256205A1 2-T SRAM CELL STRUCTURE AND METHOD 有权
标题翻译： 2-T SRAM单元结构与方法
公开(公告)号：US20090256205A1
公开(公告)日：2009-10-15
申请号：US12100441
申请日：2008-04-10
申请人： Qingqing Liang , Werner A. Rausch , Huilong Zhu
发明人： Qingqing Liang , Werner A. Rausch , Huilong Zhu
IPC分类号： H01L29/10 , G11C11/34 , H01L21/00
CPC分类号： G11C11/412 , H01L27/11 , Y10S257/903
摘要： The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.
摘要翻译：在一个实施例中，本发明提供一种存储器件，其包括包括至少一个器件区域的衬底; 具有第一阈值电压的第一场效应晶体管和具有第二阈值电压的第二场效应晶体管，所述第二场效应晶体管包括存在于所述衬底的所述至少一个器件区域中的第二有源区，所述第二有源区包括第二漏极和由第二沟道区分隔开的第二源极，其中第二沟道区包括第二陷阱，其存储当第一场效应晶体管处于导通状态时产生的空穴，其中存储在第二陷阱中的空穴增加第二阈值电压大于第一阈值电压。

4. 发明申请

US20080230840A1 ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION 有权
公开(公告)号：US20080230840A1
公开(公告)日：2008-09-25
申请号：US12132705
申请日：2008-06-04
申请人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
发明人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
IPC分类号： H01L49/00
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

5. 发明授权

US07402870B2 Ultra shallow junction formation by epitaxial interface limited diffusion 有权
标题翻译：通过外延界面限制扩散的超浅结结形成
公开(公告)号：US07402870B2
公开(公告)日：2008-07-22
申请号：US10711899
申请日：2004-10-12
申请人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
发明人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
IPC分类号： H01L29/76
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译：形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。更具体地，本发明增加了硅衬底的顶表面的氧含量。优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。这允许本发明在硅衬底的顶表面上外延生长硅层。此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

6. 发明授权

US06939751B2 Method and manufacture of thin silicon on insulator (SOI) with recessed channel 失效
标题翻译：具有凹陷通道的薄绝缘体硅（SOI）的方法和制造
公开(公告)号：US06939751B2
公开(公告)日：2005-09-06
申请号：US10605726
申请日：2003-10-22
申请人： Huilong Zhu , Bruce B. Doris , Werner A. Rausch , Ying Zhang
发明人： Huilong Zhu , Bruce B. Doris , Werner A. Rausch , Ying Zhang
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66621 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/7842 , H01L29/78687
摘要： An RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate) by the steps as follows. Form a SiGe layer over the Si layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the Si layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the Si layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions thereabove and below the level of the SiGe layer.
摘要翻译：具有凹陷沟道的RSD FET器件通过以下步骤形成有凸起的硅源和漏极以及形成在SOI结构（形成在衬底上的Si层）上的栅电极结构。在Si层上形成SiGe层，在SiGe上形成RSD层。通过RSD层和SiGe蚀刻以形成向下延伸到Si层的栅电极空间。形成一对被栅电极间隔开的RSD区域。用内部蚀刻停止层和内侧壁间隔物来排列栅电极空间的壁。在Si层上的内侧墙壁内部形成栅电极。在靠近内侧壁间隔物的RSD区域之间形成与栅电极相邻的外侧壁间隔物，并且掺杂RSD区域，由此在SOI硅层之间形成凹陷沟道，在SOI硅层之间的上升源极/漏极区域之间并且低于 SiGe层。

7. 发明授权

US06930030B2 Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness 失效
标题翻译：在硅的薄膜的表面上的凹部上形成电子器件的方法被蚀刻到精确的厚度
公开(公告)号：US06930030B2
公开(公告)日：2005-08-16
申请号：US10453080
申请日：2003-06-03
申请人： Werner A. Rausch , Tina J. Wagner , Sadanand V. Deshpande
发明人： Werner A. Rausch , Tina J. Wagner , Sadanand V. Deshpande
IPC分类号： H01L21/265 , H01L21/28 , H01L21/3065 , H01L21/3213 , H01L21/336 , H01L29/78 , H01L21/3205 , H01L21/302
CPC分类号： H01L29/66621 , H01L21/26506 , H01L21/2658 , H01L21/28114 , H01L21/3065 , H01L21/32137 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/7834
摘要： A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask. In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.
摘要翻译：用于精确稀化以在晶体硅层中形成精确深度的凹槽的方法，其可用于形成诸如MOSFET器件的各种器件，包括以下步骤。在硅层的顶表面上形成具有窗口的图案掩模。在窗口下方的硅层的顶表面形成非晶化区域。选择性地蚀刻去除硅层的非晶化区域，以在硅层表面形成凹陷，并去除图形掩模。在MOSFET器件的情况下，在图案掩模下形成硬掩模，窗口延伸穿过其中。然后通过硬掩模在窗口中产生侧壁间隔物，并在窗口中形成栅极电极堆叠。然后去除硬掩模，形成源极/漏极延伸部分，光晕和区域加上硅化物，并完成MOSFET器件。

8. 发明授权

US08680617B2 Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS 有权
标题翻译：分层式浅沟槽隔离，用于SOI MOSFET中的区域有效的体接触
公开(公告)号：US08680617B2
公开(公告)日：2014-03-25
申请号：US12574126
申请日：2009-10-06
申请人： Ying Li , Shreesh Narasimha , Werner A. Rausch
发明人： Ying Li , Shreesh Narasimha , Werner A. Rausch
IPC分类号： H01L27/12
CPC分类号： H01L29/78615 , H01L21/74 , H01L21/76229 , H01L21/76283 , H01L29/66772
摘要： Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.
摘要翻译：公开了一种体硅层上的SOI器件，其具有FET区，体接触区和STI区。 FET区域由SOI层和上覆栅极构成。 STI区域包括将SOI器件与相邻SOI器件分开的第一STI层。身体接触区域包括SOI层的延伸部，延伸部上的第二STI层和与延伸部接触的主体接触部。第一和第二STI层是连续的和不同的厚度，以便形成分级STI。

9. 发明授权

US08507915B2 Low resistance embedded strap for a trench capacitor 有权
公开(公告)号：US08507915B2
公开(公告)日：2013-08-13
申请号：US13307787
申请日：2011-11-30
申请人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L29/94
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

10. 发明授权

US07816237B2 Ultra shallow junction formation by epitaxial interface limited diffusion 有权
标题翻译：通过外延界面限制扩散的超浅结结形成
公开(公告)号：US07816237B2
公开(公告)日：2010-10-19
申请号：US12132698
申请日：2008-06-04
申请人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
发明人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译：形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。更具体地，本发明增加了硅衬底的顶表面的氧含量。优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。这允许本发明在硅衬底的顶表面上外延生长硅层。此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

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