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1. 发明授权

US08017483B2 Method of creating asymmetric field-effect-transistors 有权
标题翻译：制造不对称场效应晶体管的方法
公开(公告)号：US08017483B2
公开(公告)日：2011-09-13
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对与基底垂直。

2. 发明申请

US20100330763A1 METHOD OF CREATING ASYMMETRIC FIELD-EFFECT-TRANSISTORS 有权
标题翻译：创建不对称场效应晶体管的方法
公开(公告)号：US20100330763A1
公开(公告)日：2010-12-30
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对与基底垂直。

3. 发明授权

US08741725B2 Butted SOI junction isolation structures and devices and method of fabrication 有权
标题翻译：对接SOI结隔离结构和器件及其制造方法
公开(公告)号：US08741725B2
公开(公告)日：2014-06-03
申请号：US12943084
申请日：2010-11-10
申请人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
发明人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
IPC分类号： H01L29/06
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

4. 发明申请

US20120112280A1 BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 有权
标题翻译：所谓的SOI结隔离结构和装置以及制造方法
公开(公告)号：US20120112280A1
公开(公告)日：2012-05-10
申请号：US12943084
申请日：2010-11-10
申请人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
发明人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

5. 发明申请

US20110079851A1 SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS 有权
标题翻译： SOI MOSFET中高效地接地层分离层析
公开(公告)号：US20110079851A1
公开(公告)日：2011-04-07
申请号：US12574126
申请日：2009-10-06
申请人： YING LI , Shreesh Narasimha , Werner A. Rausch
发明人： YING LI , Shreesh Narasimha , Werner A. Rausch
IPC分类号： H01L29/06 , H01L29/772 , H01L21/762
CPC分类号： H01L29/78615 , H01L21/74 , H01L21/76229 , H01L21/76283 , H01L29/66772
摘要： Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.
摘要翻译：公开了一种体硅层上的SOI器件，其具有FET区，体接触区和STI区。 FET区域由SOI层和上覆栅极构成。 STI区域包括将SOI器件与相邻SOI器件分开的第一STI层。身体接触区域包括SOI层的延伸部，延伸部上的第二STI层和与延伸部接触的身体接触部。第一和第二STI层是连续的和不同的厚度，以便形成分级STI。

6. 发明授权

US08680617B2 Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS 有权
标题翻译：分层式浅沟槽隔离，用于SOI MOSFET中的区域有效的体接触
公开(公告)号：US08680617B2
公开(公告)日：2014-03-25
申请号：US12574126
申请日：2009-10-06
申请人： Ying Li , Shreesh Narasimha , Werner A. Rausch
发明人： Ying Li , Shreesh Narasimha , Werner A. Rausch
IPC分类号： H01L27/12
CPC分类号： H01L29/78615 , H01L21/74 , H01L21/76229 , H01L21/76283 , H01L29/66772
摘要： Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.
摘要翻译：公开了一种体硅层上的SOI器件，其具有FET区，体接触区和STI区。 FET区域由SOI层和上覆栅极构成。 STI区域包括将SOI器件与相邻SOI器件分开的第一STI层。身体接触区域包括SOI层的延伸部，延伸部上的第二STI层和与延伸部接触的主体接触部。第一和第二STI层是连续的和不同的厚度，以便形成分级STI。

7. 发明授权

US08232603B2 Gated diode structure and method including relaxed liner 有权
标题翻译：门极二极管结构及方法包括松弛衬垫
公开(公告)号：US08232603B2
公开(公告)日：2012-07-31
申请号：US12702380
申请日：2010-02-09
申请人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
发明人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
IPC分类号： H01L21/70
CPC分类号： H01L21/28518 , H01L21/76829 , H01L29/66356 , H01L29/7391
摘要： A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
摘要翻译：门控二极管结构和用于制造门控二极管结构的方法使用从应力衬里导出的松弛衬垫，其通常用于与栅极二极管结构同时形成的场效应晶体管的上下文中。复杂的衬垫与应力衬里的处理（例如离子注入处理）形成。与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。

8. 发明申请

US20100237421A1 Gated Diode Structure and Method Including Relaxed Liner 有权
标题翻译：封闭二极管结构和方法包括轻松衬里
公开(公告)号：US20100237421A1
公开(公告)日：2010-09-23
申请号：US12702380
申请日：2010-02-09
申请人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
发明人： Anthony I. Chou , Gregory G. Freeman , Kevin McStay , Shreesh Narasimha
IPC分类号： H01L27/06 , H01L21/70
CPC分类号： H01L21/28518 , H01L21/76829 , H01L29/66356 , H01L29/7391
摘要： A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
摘要翻译：门控二极管结构和用于制造门控二极管结构的方法使用从应力衬里导出的松弛衬垫，其通常用于与栅极二极管结构同时形成的场效应晶体管的上下文中。复杂的衬垫与应力衬里的处理（例如离子注入处理）形成。与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。

9. 发明授权

US08232599B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08232599B2
公开(公告)日：2012-07-31
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

10. 发明申请

US20120187492A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20120187492A1
公开(公告)日：2012-07-26
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

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