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31. 发明授权

US07888744B2 Strained semiconductor, devices and systems and methods of formation 有权
标题翻译：应变半导体，器件和系统及其形成方法
公开(公告)号：US07888744B2
公开(公告)日：2011-02-15
申请号：US12346281
申请日：2008-12-30
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/76232 , H01L29/6659 , H01L29/7833
摘要： In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，器件区域被限定在半导体衬底中，并且隔离区域被限定为与器件区域相邻。器件区域具有通道区域，隔离区域具有体积。调整隔离区的体积以提供具有所需应变的通道区。在各种实施例中，调节隔离区域的体积包括将隔离区域从结晶区域转换为非晶区域以扩大隔离区域的体积并且为通道区域提供期望的压缩应变。在各种实施例中，调节隔离区域的体积包括将隔离区域从非晶区域转换为结晶区域以收缩隔离区域的体积，以提供具有期望拉伸应变的通道区域。本文提供了其它方面和实施例。

32. 发明授权

US07674698B2 Metal-substituted transistor gates 失效
标题翻译：金属取代晶体管栅极
公开(公告)号：US07674698B2
公开(公告)日：2010-03-09
申请号：US11444993
申请日：2006-06-01
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L21/336
CPC分类号： H01L21/02164 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/28079 , H01L21/28194 , H01L21/28229 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L2924/0002 , Y10S438/926 , Y10T428/12354 , H01L2924/00
摘要： One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors is formed. For each transistor, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. At least two substitution processes are performed. Each substitution process includes substituting a desired gate material for the substitutable structure. Other aspects and embodiments are provided herein.
摘要翻译：本公开的一个方面涉及一种用于形成集成电路的方法。根据该方法的各种实施例，形成多个晶体管。对于每个晶体管，在衬底上形成栅极电介质，在栅极电介质上形成可取代的结构，并且形成用于晶体管的源/漏区。至少执行两个替换过程。每个取代过程包括用期望的栅极材料代替可替代结构。本文提供了其它方面和实施例。

33. 发明授权

US07541081B2 Phase change memory for archival data storage 有权
标题翻译：用于存档数据存储的相变存储器
公开(公告)号：US07541081B2
公开(公告)日：2009-06-02
申请号：US11190014
申请日：2005-07-27
申请人： Paul A. Farrar , Leonard Forbes , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Alan R. Reinberg
IPC分类号： B32B3/02
CPC分类号： G11B7/2595 , G11B7/00455 , G11B7/24038 , G11B7/243
摘要： A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a plurality of low reflectance portions comprising a mixture of a noble metal and an underlying material. The plurality of low reflectance portions have top surfaces comprising a compound of the underlying and the noble metal. A method of changing reflectance on a data storage disk is also disclosed. The method comprises the acts of irradiating a laser light beam onto a noble metal formed over an underlying layer, and raising the temperature of the noble metal above the melting temperature forming a compound of the noble metal and the underlying material.
摘要翻译：提供了一种用于存储数字数据的结构，其中包括形成在下层材料层上的贵金属的高反射率层和包含贵金属和下层材料的混合物的多个低反射率部分。多个低反射率部分具有包括底层和贵金属的化合物的顶表面。还公开了一种在数据存储盘上改变反射率的方法。该方法包括将激光照射到形成在下层上的贵金属上的动作，并将贵金属的温度升高到高于贵金属和底层材料的化合物的熔融温度。

34. 发明申请

US20080277734A1 IMPLANTATION PROCESSES FOR STRAINING TRANSISTOR CHANNELS OF SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICES WITH STRAINED TRANSISTOR CHANNELS 有权
标题翻译：用于应变半导体器件结构的晶体管通道的施加过程和具有应变晶体管通道的半导体器件
公开(公告)号：US20080277734A1
公开(公告)日：2008-11-13
申请号：US11745814
申请日：2007-05-08
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/80 , H01L21/8238
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/66492 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavties, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
摘要翻译：本发明包括用于应力半导体器件结构的晶体管沟道的方法。这样的方法包括形成邻近源极/漏极区域的所谓的近表面“纳米空腔”，形成与纳米空间相邻并包括纳米空间的源极/漏极区域的延伸部分，以及将扩大或收缩纳米孔隙的类型的植入物质分别取决于纳米空间中的晶体管通道中是否压缩应变，如PMOS场效应晶体管中的压应变，或晶体管通道中的拉伸应变，如在NMOS场效应晶体管中，以增强载流子迁移率和晶体管速度。还公开了包括这些特征的半导体器件结构和半导体器件。

35. 发明申请

US20080042211A1 Strained semiconductor channels and methods of formation 有权
标题翻译：应变半导体通道和形成方法
公开(公告)号：US20080042211A1
公开(公告)日：2008-02-21
申请号：US11506986
申请日：2006-08-18
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/7621 , H01L21/76232 , H01L29/0653 , H01L29/66568 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，限定半导体衬底中的器件区域和与器件区域相邻的隔离区域。器件区域具有沟道区域，并且隔离区域具有与沟道区域横向相邻的应变诱导区域。通道区域应变为用于载流子迁移率增强的期望应变，其中至少一种离子型注入能量，从而在隔离区域的应变诱导区域中产生峰值注入。本文提供了其它方面和实施例。

36. 发明授权

US07300821B2 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US07300821B2
公开(公告)日：2007-11-27
申请号：US10930252
申请日：2004-08-31
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

37. 发明授权

US06377156B2 High-Q inductive elements 有权
公开(公告)号：US06377156B2
公开(公告)日：2002-04-23
申请号：US09867281
申请日：2001-05-29
申请人： Paul A. Farrar , Leonard Forbes
发明人： Paul A. Farrar , Leonard Forbes
IPC分类号： H01F500
CPC分类号： H01L28/10 , H01F41/041 , H01L27/08
摘要： A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via hole. A second conductor is formed on the second insulator, and is electrically coupled to the first conductor by the via hole. The second conductor is patterned. A cavity is formed under the second conductor, and in the first and second insulators.

38. 发明授权

US06376895B2 High-Q inductive elements 有权
标题翻译：高Q电感元件
公开(公告)号：US06376895B2
公开(公告)日：2002-04-23
申请号：US09467991
申请日：1999-12-20
申请人： Paul A. Farrar , Leonard Forbes
发明人： Paul A. Farrar , Leonard Forbes
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01F41/041 , H01L27/08
摘要： A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via hole. A second conductor is formed on the second insulator, and is electrically coupled to the first conductor by the via hole. The second conductor is patterned. A cavity is formed under the second conductor, and in the first and second insulators.
摘要翻译：第一绝缘体形成在基层上。在第一绝缘体上形成第一导体。第一根导体被图案化。在第一绝缘体上形成第二绝缘体。通孔形成在第二绝缘体中，并通过通孔与第一导体电耦合。第二导体形成在第二绝缘体上，并且通过通孔与第一导体电耦合。第二导体被图案化。在第二导体下面形成空腔，在第一和第二绝缘体中形成空腔。

39. 发明授权

US06356500B1 Reduced power DRAM device and method 有权
标题翻译：降低功耗的DRAM器件和方法
公开(公告)号：US06356500B1
公开(公告)日：2002-03-12
申请号：US09643945
申请日：2000-08-23
申请人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
发明人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C5/14 , G11C11/4074
摘要： A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
摘要翻译：公开了一种采用降低功耗的方案的存储器件和方法。通过将存储器阵列扇区划分成存储器子阵列，存储器件可以为需要上电的存储器子阵列或替代地断电提供电力。这降低了与高速和高容量存储器件相关联的功耗和发热。

40. 发明授权

US09929229B2 Process of manufacturing an open pattern inductor 有权
公开(公告)号：US09929229B2
公开(公告)日：2018-03-27
申请号：US13219459
申请日：2011-08-26
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01F41/04 , H01F17/00 , H01L49/02 , H01L27/08 , H01P11/00 , H01P9/02 , H01F27/36
CPC分类号： H01L28/10 , H01F17/0013 , H01F27/365 , H01F41/043 , H01F41/046 , H01L27/08 , H01P9/02 , H01P11/007 , Y10T29/4902 , Y10T29/4906 , Y10T29/49062 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075
摘要： Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may include a magnetic material directly contacts one of the conducting patterns and the substrate. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

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