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1. 发明授权

US08507341B2 Integrated circuit fabrication 有权
公开(公告)号：US08507341B2
公开(公告)日：2013-08-13
申请号：US13445797
申请日：2012-04-12
申请人： Luan C. Tran , John Lee , Zengtao “Tony” Liu , Eric Freeman , Russell Nielsen
发明人： Luan C. Tran , John Lee , Zengtao “Tony” Liu , Eric Freeman , Russell Nielsen
IPC分类号： H01L21/8242
CPC分类号： H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3083 , H01L21/31144 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/544 , H01L27/1052 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

2. 发明申请

US20130113061A1 IMAGE SENSOR TRENCH ISOLATION WITH CONFORMAL DOPING 有权
公开(公告)号：US20130113061A1
公开(公告)日：2013-05-09
申请号：US13290733
申请日：2011-11-07
申请人： Chih-Yu Lai , Yeur-Luen Tu , Chih-Hui Huang , Cheng-Ta Wu , Chia-Shiung Tsai , Luan C. Tran
发明人： Chih-Yu Lai , Yeur-Luen Tu , Chih-Hui Huang , Cheng-Ta Wu , Chia-Shiung Tsai , Luan C. Tran
IPC分类号： H01L27/146 , H01L31/18 , H01L31/0232
CPC分类号： H01L27/1463 , H01L21/02129 , H01L21/223 , H01L21/2255 , H01L21/76224 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L31/09
摘要： Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner.

3. 发明申请

US20120193777A1 INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：集成电路制造
公开(公告)号：US20120193777A1
公开(公告)日：2012-08-02
申请号：US13445797
申请日：2012-04-12
申请人： Luan C. Tran , John Lee , Zengtao "Tony" Liu , Eric Freeman , Russell Nielsen
发明人： Luan C. Tran , John Lee , Zengtao "Tony" Liu , Eric Freeman , Russell Nielsen
IPC分类号： H01L23/52
CPC分类号： H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3083 , H01L21/31144 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/544 , H01L27/1052 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
摘要翻译：用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。下掩蔽层中的特征包括环形端。该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。沟槽具有沟槽宽度。

4. 发明申请

US20110285029A1 SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS 有权
标题翻译：半导体结构包括轻触式触点
公开(公告)号：US20110285029A1
公开(公告)日：2011-11-24
申请号：US13194558
申请日：2011-07-29
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L23/48 , B82Y99/00
CPC分类号： H01L21/76802 , H01L21/02164 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/3141 , H01L21/31608 , H01L21/7681 , H01L21/76816 , H01L21/76877 , H01L23/481 , H01L27/108 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
摘要翻译：制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

5. 发明申请

US20100289070A1 METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES 有权
标题翻译：隔离多孔材料环的分离方法及相关结构
公开(公告)号：US20100289070A1
公开(公告)日：2010-11-18
申请号：US12845167
申请日：2010-07-28
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L27/088 , H01L29/788 , H01L29/06
CPC分类号： H01L21/76816 , H01L21/02518 , H01L21/0337 , H01L21/0338 , H01L21/28273 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L27/0705 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/66477 , H01L29/66825 , H01L29/788
摘要： Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.
摘要翻译：半导体材料的连续环路的不同部分彼此电隔离。在一些实施例中，环路的端部与环路的中间部分电隔离。在一些实施例中，具有在其端部连接在一起的两个腿的半导体材料的环通过间距倍增过程形成，其中间隔物的环形成在心轴的侧壁上。去除心轴并且将一块掩模材料覆盖在间隔环的至少一端上。在一些实施例中，掩模材料块覆盖间隔环的每一端。由间隔物和块限定的图案被转移到半导体材料层。这些块将所有环路电连接在一起。沿循环的每条腿形成选择门。这些块作为源/排水沟。选择门被偏置在关闭状态以防止电流从环路的中部流向块，从而将中间部分与环的端部电隔离，并且还将环的不同的腿与每个其他。

6. 发明授权

US07518184B2 DRAM access transistor 失效
标题翻译： DRAM存取晶体管
公开(公告)号：US07518184B2
公开(公告)日：2009-04-14
申请号：US11474362
申请日：2006-06-26
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L29/76
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10811 , H01L27/10891 , H01L29/42376 , H01L29/66621 , H01L29/7834 , H01L29/7835
摘要： Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.
摘要翻译：公开了自对准凹陷门结构和形成方法。首先在半导体衬底中形成用于隔离的场氧化物区域。多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。

7. 发明授权

US07365384B2 Trench buried bit line memory devices and methods thereof 有权
标题翻译：沟槽掩埋位线存储器件及其方法
公开(公告)号：US07365384B2
公开(公告)日：2008-04-29
申请号：US11588748
申请日：2006-10-27
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
摘要翻译：存储器件包括大致平行于并沿着有源区域的相关带形成的隔离沟槽。导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

8. 发明授权

US07321149B2 Capacitor structures, and DRAM arrays 有权
标题翻译：电容结构和DRAM阵列
公开(公告)号：US07321149B2
公开(公告)日：2008-01-22
申请号：US11187210
申请日：2005-07-22
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Richard D. Holscher
IPC分类号： H01L29/72
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

9. 发明授权

US07279379B2 Methods of forming memory arrays; and methods of forming contacts to bitlines 有权
标题翻译：形成存储器阵列的方法以及形成与位线的接触的方法
公开(公告)号：US07279379B2
公开(公告)日：2007-10-09
申请号：US10832543
申请日：2004-04-26
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/00
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

10. 发明授权

US07253047B2 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry 有权
标题翻译：形成晶体管的半导体处理方法，形成动态随机存取存储器电路的半导体处理方法以及相关的集成电路
公开(公告)号：US07253047B2
公开(公告)日：2007-08-07
申请号：US09388857
申请日：1999-09-01
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L21/00
CPC分类号： H01L21/823481 , H01L27/10894 , H01L27/10897
摘要： Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. In one embodiment, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors.
摘要翻译：描述形成晶体管的半导体处理方法，形成动态随机存取存储器电路的半导体处理方法以及相关的集成电路。在一个实施例中，有源区域形成在衬底上，其中一个有源区域具有小于1微米的宽度，并且一些有源区域具有不同的宽度。在有源区上形成栅极线以提供具有不同阈值电压的晶体管。在一个实施例中，晶体管被提供有不同的阈值电压，而不使用用于晶体管的单独沟道注入。

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