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1. 发明授权

US07492042B2 Integrated circuit cooling and insulating device and method 失效
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07492042B2
公开(公告)日：2009-02-17
申请号：US11977515
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

2. 发明授权

US06456535B2 Dynamic flash memory cells with ultra thin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06456535B2
公开(公告)日：2002-09-24
申请号：US09882920
申请日：2001-06-15
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

3. 发明授权

US06249460B1 Dynamic flash memory cells with ultrathin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06249460B1
公开(公告)日：2001-06-19
申请号：US09513938
申请日：2000-02-28
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

4. 发明授权

US07485497B2 Integrated circuit cooling and insulating device and method 失效
公开(公告)号：US07485497B2
公开(公告)日：2009-02-03
申请号：US11977524
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

5. 发明授权

US07304380B2 Integrated circuit cooling and insulating device and method 有权
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07304380B2
公开(公告)日：2007-12-04
申请号：US11482308
申请日：2006-07-07
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

6. 发明授权

US07541081B2 Phase change memory for archival data storage 有权
标题翻译：用于存档数据存储的相变存储器
公开(公告)号：US07541081B2
公开(公告)日：2009-06-02
申请号：US11190014
申请日：2005-07-27
申请人： Paul A. Farrar , Leonard Forbes , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Alan R. Reinberg
IPC分类号： B32B3/02
CPC分类号： G11B7/2595 , G11B7/00455 , G11B7/24038 , G11B7/243
摘要： A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a plurality of low reflectance portions comprising a mixture of a noble metal and an underlying material. The plurality of low reflectance portions have top surfaces comprising a compound of the underlying and the noble metal. A method of changing reflectance on a data storage disk is also disclosed. The method comprises the acts of irradiating a laser light beam onto a noble metal formed over an underlying layer, and raising the temperature of the noble metal above the melting temperature forming a compound of the noble metal and the underlying material.
摘要翻译：提供了一种用于存储数字数据的结构，其中包括形成在下层材料层上的贵金属的高反射率层和包含贵金属和下层材料的混合物的多个低反射率部分。多个低反射率部分具有包括底层和贵金属的化合物的顶表面。还公开了一种在数据存储盘上改变反射率的方法。该方法包括将激光照射到形成在下层上的贵金属上的动作，并将贵金属的温度升高到高于贵金属和底层材料的化合物的熔融温度。

7. 发明授权

US07300821B2 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US07300821B2
公开(公告)日：2007-11-27
申请号：US10930252
申请日：2004-08-31
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

8. 发明授权

US06356500B1 Reduced power DRAM device and method 有权
标题翻译：降低功耗的DRAM器件和方法
公开(公告)号：US06356500B1
公开(公告)日：2002-03-12
申请号：US09643945
申请日：2000-08-23
申请人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
发明人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C5/14 , G11C11/4074
摘要： A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
摘要翻译：公开了一种采用降低功耗的方案的存储器件和方法。通过将存储器阵列扇区划分成存储器子阵列，存储器件可以为需要上电的存储器子阵列或替代地断电提供电力。这降低了与高速和高容量存储器件相关联的功耗和发热。

9. 发明申请

US20100055871A1 MEMORY IN LOGIC CELL 有权
标题翻译：存储在逻辑单元
公开(公告)号：US20100055871A1
公开(公告)日：2010-03-04
申请号：US12615961
申请日：2009-11-10
申请人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
发明人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
IPC分类号： H01L21/28 , H01L21/30
CPC分类号： G11C16/0408 , H01L21/28273 , H01L27/11803 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.
摘要翻译：提供了逻辑单元中存储器的方法，设备和系统。一个或多个实施例包括使用具有第一栅极，第二栅极和第三栅极（例如，控制栅极，背栅极和浮置栅极）的单元结构作为逻辑单元中的存储器。该方法包括将浮动栅极编程为第一状态以使逻辑单元中的存储器作为第一逻辑门类型工作。该方法还包括将浮动栅极编程到第二状态以使逻辑单元中的存储器作为第二逻辑门类型工作。

10. 发明申请

US20080316828A1 Memory in logic cell 有权
标题翻译：内存在逻辑单元格中
公开(公告)号：US20080316828A1
公开(公告)日：2008-12-25
申请号：US11821462
申请日：2007-06-21
申请人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
发明人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
IPC分类号： G11C11/34 , H01L21/336
CPC分类号： G11C16/0408 , H01L21/28273 , H01L27/11803 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.
摘要翻译：提供了逻辑单元中存储器的方法，设备和系统。一个或多个实施例包括使用具有第一栅极，第二栅极和第三栅极（例如，控制栅极，背栅极和浮置栅极）的单元结构作为逻辑单元中的存储器。该方法包括将浮动栅极编程为第一状态以使逻辑单元中的存储器作为第一逻辑门类型工作。该方法还包括将浮动栅极编程到第二状态以使逻辑单元中的存储器作为第二逻辑门类型工作。

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