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1. 发明授权

US09129961B2 Gallium lathanide oxide films 有权
标题翻译：柠檬酸铅氧化膜
公开(公告)号：US09129961B2
公开(公告)日：2015-09-08
申请号：US13175551
申请日：2011-07-01
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L29/51 , H01L21/02 , H01L21/314 , C23C16/40 , C23C16/455 , H01L21/28 , H01L21/316 , H01L49/02 , H01L29/10 , H01L29/788 , H01L21/8238
CPC分类号： H01L21/02194 , C23C16/40 , C23C16/45531 , H01L21/02192 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31604 , H01L21/823857 , H01L28/40 , H01L28/56 , H01L29/1033 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的镓镧系氧化物膜。镓镧系氧化物膜可以被构造成一个或多个单层。镓镧系氧化物膜可以使用原子层沉积形成。

2. 发明授权

US08962447B2 Bonded strained semiconductor with a desired surface orientation and conductance direction 有权
标题翻译：具有期望的表面取向和电导方向的结合的应变半导体
公开(公告)号：US08962447B2
公开(公告)日：2015-02-24
申请号：US11498586
申请日：2006-08-03
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： H01L21/30 , H01L21/46 , H01L21/8238 , H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/045 , H01L29/1037 , H01L29/66651 , H01L29/7843 , H01L29/7849
摘要： According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein.
摘要翻译：根据各种方法实施例，半导体层被定向到衬底。半导体层具有表面取向并且被定向到衬底以提供用于表面取向的期望的电导方向。取向半导体层与基板结合以使半导体层变形。各种实施例提供拉伸应变，并且各种实施例提供压缩应变。本文提供了其它方面和实施例。

3. 发明授权

US08786006B2 Flash memory device having a graded composition, high dielectric constant gate insulator 有权
标题翻译：具有渐变组成的闪存器件，高介电常数栅极绝缘体
公开(公告)号：US08786006B2
公开(公告)日：2014-07-22
申请号：US13595219
申请日：2012-08-27
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L29/78 , H01L27/115 , H01L21/8239
CPC分类号： H01L27/11517 , H01L21/8239 , H01L27/11563 , H01L29/513 , H01L29/7881
摘要： A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.
摘要翻译：在闪速存储单元晶体管中的衬底和浮置栅极之间形成分级成分，高介电常数栅极绝缘体。栅极绝缘体包括无定形锗或碳化锗和碳化硅的分级组合物。如果栅极绝缘体的组成更靠近基板附近的碳化硅，则热电子注入的电子势垒将更低。如果栅极绝缘体靠近浮动栅极附近的碳化硅，隧道势垒可以在浮动栅极处较低。

4. 发明授权

US08765616B2 Zirconium-doped tantalum oxide films 有权
标题翻译：掺锆氧化钽薄膜
公开(公告)号：US08765616B2
公开(公告)日：2014-07-01
申请号：US13618212
申请日：2012-09-14
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/31 , H01L21/469 , H01L21/00 , H01L21/16
CPC分类号： H01L21/0228 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02183 , H01L21/02189 , H01L21/02194 , H01L21/02321 , H01L21/3141 , H01L21/31637 , H01L21/31641
摘要： Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
摘要翻译：含有锆掺杂的钽氧化物层的介电层，其中掺锆的钽氧化物层可以由掺杂有锆的一个或多个单层钽氧化物形成，提供各种结构的绝缘层，用于广泛的电子设备。

5. 发明授权

US08741746B2 Silicon on germanium 有权
标题翻译：锗在锗上
公开(公告)号：US08741746B2
公开(公告)日：2014-06-03
申请号：US13617211
申请日：2012-09-14
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/20 , H01L21/36 , H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L29/78651 , H01L21/28255 , H01L29/513 , H01L29/517
摘要： A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
摘要翻译：可以使用单层或部分单层测序处理，例如原子层沉积（ALD），以在锗衬底上形成硅膜的半导体结构。这种结构在高性能电子设备中可能是有用的。可以通过在锗衬底表面上沉积薄硅层，形成氧化铪介电层并形成氮化钽电极来形成结构。电介质的性质可以通过用另一电介质如氧化锆或氧化钛代替氧化铪来改变。

6. 发明授权

US08628615B2 Titanium-doped indium oxide films 有权
标题翻译：钛掺杂氧化铟膜
公开(公告)号：US08628615B2
公开(公告)日：2014-01-14
申请号：US13615906
申请日：2012-09-14
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： C30B23/02
CPC分类号： C30B29/16 , C23C16/407 , C23C16/45531 , C30B25/16
摘要： An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition.
摘要翻译：形成该装置的装置和方法包括用于各种配置和系统的透明导电钛掺杂氧化铟薄膜。透明导电性钛掺杂氧化铟的膜可以被构造为一个或多个单层。可以使用原子层沉积形成透明导电性钛掺杂氧化铟的膜。

7. 发明授权

US08466016B2 Hafnium tantalum oxynitride dielectric 有权
标题翻译：铪钽氧氮化物电介质
公开(公告)号：US08466016B2
公开(公告)日：2013-06-18
申请号：US13332222
申请日：2011-12-20
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L21/338
CPC分类号： G11C16/0466 , H01L21/3142 , H01L21/31637 , H01L21/31645 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66545
摘要： Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.
摘要翻译：电子设备和方法可以包括用于各种电子系统的基板上的铪钽氮化物膜。铪钽氮氧化物膜可以被构造为一个或多个单层。可以使用原子层沉积形成氮氧化钽铪膜。金属电极可以设置在含有铪钽氮氧化物膜的电介质上。

8. 发明授权

US08354738B2 Structures including passivated germanium 失效
标题翻译：结构包括钝化锗
公开(公告)号：US08354738B2
公开(公告)日：2013-01-15
申请号：US13072182
申请日：2011-03-25
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L29/06
CPC分类号： H01L29/167 , H01L31/1808 , H01L31/1812 , Y02E10/50
摘要： A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.
摘要翻译：钝化的锗表面，其是在锗材料上形成并与锗材料接触的碳化锗材料。还公开了一种中间半导体器件结构和半导体器件结构，其中每个包括其上具有碳化锗材料的钝化锗。

9. 发明授权

US08350320B2 Memory array and memory device 有权
标题翻译：内存阵列和内存设备
公开(公告)号：US08350320B2
公开(公告)日：2013-01-08
申请号：US13352652
申请日：2012-01-18
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66477 , G11C7/18 , G11C2207/002 , H01L27/10876
摘要： A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.
摘要翻译：具有交错的本地数据/位线的存储器阵列，其大致沿着形成在衬底的上表面中的第一方向延伸，并且大体向上延伸并且大致对准相应的本地数据/位线的存储单元存取晶体管。牺牲存储单元存取晶体管的选定列以定义与叠加的低电阻全局数据/位线互连的本地数据/位存取晶体管。全局数据/位线在存储器单元和读出放大器之间提供可选择的低电阻路径。牺牲的存储单元访问晶体管和交错的局部数据/位线为读出放大器提供了增加的占位面积，以便于增加电路集成。

10. 发明申请

US20130001575A1 METHODS FOR STRESSING TRANSISTOR CHANNELS OF A SEMICONDUCTOR DEVICE STRUCTURE, AND A RELATED SEMICONDUCTOR DEVICE STRUCTURE 有权
标题翻译：用于压制半导体器件结构的晶体管通道的方法和相关的半导体器件结构
公开(公告)号：US20130001575A1
公开(公告)日：2013-01-03
申请号：US13611249
申请日：2012-09-12
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/66492 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
摘要翻译：本发明包括用于应力半导体器件结构的晶体管沟道的方法。这种方法包括形成邻近源极/漏极区域的所谓近表面纳米孔，形成邻近并包括纳米孔的源极/漏极区域的延伸部分，以及将扩大或收缩体积的类型的植入物质分别取决于在NMOS场效应晶体管中如在NMOS场效应晶体管中在纳米腔中的晶体管通道中是否需要压缩应变，如在PMOS场效应晶体管中的拉伸应变或拉伸应变，以增强载流子迁移率和晶体管速度。还公开了包括这些特征的半导体器件结构和半导体器件。

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