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1. 发明授权

US06356500B1 Reduced power DRAM device and method 有权
标题翻译：降低功耗的DRAM器件和方法
公开(公告)号：US06356500B1
公开(公告)日：2002-03-12
申请号：US09643945
申请日：2000-08-23
申请人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
发明人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C5/14 , G11C11/4074
摘要： A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
摘要翻译：公开了一种采用降低功耗的方案的存储器件和方法。通过将存储器阵列扇区划分成存储器子阵列，存储器件可以为需要上电的存储器子阵列或替代地断电提供电力。这降低了与高速和高容量存储器件相关联的功耗和发热。

2. 发明授权

US06456535B2 Dynamic flash memory cells with ultra thin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06456535B2
公开(公告)日：2002-09-24
申请号：US09882920
申请日：2001-06-15
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

3. 发明授权

US06249460B1 Dynamic flash memory cells with ultrathin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06249460B1
公开(公告)日：2001-06-19
申请号：US09513938
申请日：2000-02-28
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

4. 发明授权

US07485497B2 Integrated circuit cooling and insulating device and method 失效
公开(公告)号：US07485497B2
公开(公告)日：2009-02-03
申请号：US11977524
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

5. 发明授权

US07304380B2 Integrated circuit cooling and insulating device and method 有权
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07304380B2
公开(公告)日：2007-12-04
申请号：US11482308
申请日：2006-07-07
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

6. 发明授权

US07492042B2 Integrated circuit cooling and insulating device and method 失效
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07492042B2
公开(公告)日：2009-02-17
申请号：US11977515
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

7. 发明授权

US07300821B2 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US07300821B2
公开(公告)日：2007-11-27
申请号：US10930252
申请日：2004-08-31
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

8. 发明授权

US06541859B1 Methods and structures for silver interconnections in integrated circuits 有权
标题翻译：集成电路中银互连的方法和结构
公开(公告)号：US06541859B1
公开(公告)日：2003-04-01
申请号：US09614492
申请日：2000-07-11
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/32055 , H01L21/7682 , H01L23/53242 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new “self-trenching” or “self-planarizing” method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.
摘要翻译：典型的集成电路制造需要使用铝线连接数以百万计的微观晶体管和电阻器。使铝线与底层绝缘层齐平或共面需要在绝缘层中挖沟，然后用铝填充沟槽以形成铝线。沟槽挖掘费时费力。此外，铝比其他金属（例如银）具有更高的电阻。因此，本发明提供了制造共面银线的新的“自挖沟”或“自平面化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使银与非氧化区反应。反应用银代替或替代未氧化区域，以形成与第一层共面的银线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。因此，本发明不仅消除了常规方法的耗时的沟槽挖掘步骤，而且还降低了电阻和电容，进而实现了更快，更高效的集成电路。

9. 发明授权

US6143655A Methods and structures for silver interconnections in integrated circuits 失效
公开(公告)号：US6143655A
公开(公告)日：2000-11-07
申请号：US30113
申请日：1998-02-25
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/532 , H01L21/00 , H01L21/44 , H01L29/40
CPC分类号： H01L21/76877 , H01L21/32055 , H01L21/7682 , H01L23/53242 , H01L23/53252 , H01L2924/0002
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.

10. 发明授权

US6100176A Methods and structures for gold interconnections in integrated circuits 有权
标题翻译：集成电路中金互连的方法和结构
公开(公告)号：US6100176A
公开(公告)日：2000-08-08
申请号：US188970
申请日：1998-11-10
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L23/532 , H01L21/764
CPC分类号： H01L23/53252 , H01L23/53242 , H01L2924/0002
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as gold. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar gold wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts gold with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with gold to form gold wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.
摘要翻译：典型的集成电路制造需要使用铝线连接数以百万计的微观晶体管和电阻器。使铝线与底层绝缘层齐平或共面需要在绝缘层中挖沟，然后用铝填充沟槽以形成铝线。沟槽挖掘费时费力。此外，铝比其他金属（例如金）具有更高的电阻。因此，本发明提供了一种制造共面金线的新型“自挖沟”或“自平面化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使金与非氧化区反应。反应用金取代或取代未氧化区域，形成与第一层共面的金线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。因此，本发明不仅消除了常规方法的耗时的沟槽挖掘步骤，而且还降低了电阻和电容，进而实现了更快，更高效的集成电路。

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