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1. 发明申请

US20130001575A1 METHODS FOR STRESSING TRANSISTOR CHANNELS OF A SEMICONDUCTOR DEVICE STRUCTURE, AND A RELATED SEMICONDUCTOR DEVICE STRUCTURE 有权
标题翻译：用于压制半导体器件结构的晶体管通道的方法和相关的半导体器件结构
公开(公告)号：US20130001575A1
公开(公告)日：2013-01-03
申请号：US13611249
申请日：2012-09-12
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/66492 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
摘要翻译：本发明包括用于应力半导体器件结构的晶体管沟道的方法。这种方法包括形成邻近源极/漏极区域的所谓近表面纳米孔，形成邻近并包括纳米孔的源极/漏极区域的延伸部分，以及将扩大或收缩体积的类型的植入物质分别取决于在NMOS场效应晶体管中如在NMOS场效应晶体管中在纳米腔中的晶体管通道中是否需要压缩应变，如在PMOS场效应晶体管中的拉伸应变或拉伸应变，以增强载流子迁移率和晶体管速度。还公开了包括这些特征的半导体器件结构和半导体器件。

2. 发明授权

US07968960B2 Methods of forming strained semiconductor channels 有权
标题翻译：形成应变半导体通道的方法
公开(公告)号：US07968960B2
公开(公告)日：2011-06-28
申请号：US11506986
申请日：2006-08-18
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/76 , H01L21/425
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/7621 , H01L21/76232 , H01L29/0653 , H01L29/66568 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，限定半导体衬底中的器件区域和与器件区域相邻的隔离区域。器件区域具有沟道区域，并且隔离区域具有与沟道区域横向相邻的应变诱导区域。通道区域应变为用于载流子迁移率增强的期望应变，其中至少一种离子型注入能量，从而在隔离区域的应变诱导区域中产生峰值注入。本文提供了其它方面和实施例。

3. 发明申请

US20090108363A1 STRAINED SEMICONDUCTOR, DEVICES AND SYSTEMS AND METHODS OF FORMATION 有权
标题翻译：应变半导体，器件和系统及其形成方法
公开(公告)号：US20090108363A1
公开(公告)日：2009-04-30
申请号：US12346281
申请日：2008-12-30
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： H01L27/088 , H01L29/06
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/76232 , H01L29/6659 , H01L29/7833
摘要： In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，器件区域被限定在半导体衬底中，并且隔离区域被限定为与器件区域相邻。器件区域具有通道区域，隔离区域具有体积。调整隔离区的体积以提供具有所需应变的通道区。在各种实施例中，调节隔离区域的体积包括将隔离区域从结晶区域转换为非晶区域以扩大隔离区域的体积并且为通道区域提供期望的压缩应变。在各种实施例中，调节隔离区域的体积包括将隔离区域从非晶区域转换为结晶区域以收缩隔离区域的体积，以提供具有期望拉伸应变的通道区域。本文提供了其它方面和实施例。

4. 发明授权

US07485497B2 Integrated circuit cooling and insulating device and method 失效
公开(公告)号：US07485497B2
公开(公告)日：2009-02-03
申请号：US11977524
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

5. 发明授权

US07411823B2 In-service reconfigurable DRAM and flash memory device 有权
标题翻译：在服务可重新配置的DRAM和闪存设备
公开(公告)号：US07411823B2
公开(公告)日：2008-08-12
申请号：US11435620
申请日：2006-05-17
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： G11C11/34
CPC分类号： G11C14/00 , G11C11/404 , G11C11/405 , G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10894 , H01L27/11526 , H01L27/11531 , H01L27/11534 , H01L27/11568
摘要： A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.
摘要翻译：具有DRAM单元和非易失性存储单元的存储单元。非易失性存储单元可以包括闪存或NROM单元。存储单元包括具有双栅极的垂直浮体晶体管，一个在衬底的垂直柱的两侧。一个栅极是与晶体管的浮体相邻并用作DRAM单元的多晶硅栅极和栅极绝缘体。该非易失性存储单元构造在具有浮动栅极或NROM结构的柱体的另一侧上。 DRAM和非易失性单元通过将两个单元耦合到存储器阵列位线的漏极区域链接。柱的任一侧的沟槽的底部具有与存储器阵列的各个源极线相连的源极区域。

6. 发明授权

US07359241B2 In-service reconfigurable DRAM and flash memory device 有权
公开(公告)号：US07359241B2
公开(公告)日：2008-04-15
申请号：US11435621
申请日：2006-05-17
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： G11C11/34
CPC分类号： G11C14/00 , G11C11/404 , G11C11/405 , G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10894 , H01L27/11526 , H01L27/11531 , H01L27/11534 , H01L27/11568
摘要： A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.

7. 发明申请

US20080029840A1 Strained semiconductor, devices and systems and methods of formation 有权
标题翻译：应变半导体，器件和系统及其形成方法
公开(公告)号：US20080029840A1
公开(公告)日：2008-02-07
申请号：US11497632
申请日：2006-08-02
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/00
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/76232 , H01L29/6659 , H01L29/7833
摘要： In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，器件区域被限定在半导体衬底中，并且隔离区域被限定为与器件区域相邻。器件区域具有通道区域，隔离区域具有体积。调整隔离区的体积以提供具有所需应变的通道区。在各种实施例中，调节隔离区域的体积包括将隔离区域从结晶区域转换为非晶区域以扩大隔离区域的体积并且为通道区域提供期望的压缩应变。在各种实施例中，调节隔离区域的体积包括将隔离区域从非晶区域转换为结晶区域以收缩隔离区域的体积，以提供具有期望拉伸应变的通道区域。本文提供了其它方面和实施例。

8. 发明授权

US07304380B2 Integrated circuit cooling and insulating device and method 有权
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07304380B2
公开(公告)日：2007-12-04
申请号：US11482308
申请日：2006-07-07
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

9. 发明授权

US06879017B2 Methods and structures for metal interconnections in integrated circuits 有权
标题翻译：集成电路中金属互连的方法和结构
公开(公告)号：US06879017B2
公开(公告)日：2005-04-12
申请号：US10338178
申请日：2003-01-07
申请人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
发明人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/768 , H01L23/532 , H01L29/00
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.
摘要翻译：典型的集成电路制造需要用金属线互连数百万个微观晶体管和电阻器。使金属丝与底层绝缘体齐平或共面需要在绝缘层中挖沟，然后用金属填充沟槽以形成导线。本发明提供了一种制造共面金属线的新的“无沟槽”或“自平坦化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使铝或铝合金与非氧化区域反应。该反应用铝代替或替代非氧化区域以形成与第一层共面的金属线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。

10. 发明授权

US06239684B1 High-Q inductive elements 有权
标题翻译：高Q电感元件
公开(公告)号：US06239684B1
公开(公告)日：2001-05-29
申请号：US09460655
申请日：1999-12-14
申请人： Paul A. Farrar , Leonard Forbes
发明人： Paul A. Farrar , Leonard Forbes
IPC分类号： H01F500
CPC分类号： H01L28/10 , H01F41/041 , H01L27/08
摘要： A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via hole. A second conductor is formed on the second insulator, and is electrically coupled to the first conductor by the via hole. The second conductor is patterned. A cavity is formed under the second conductor, and in the first and second insulators.
摘要翻译：第一绝缘体形成在基层上。在第一绝缘体上形成第一导体。第一根导体被图案化。在第一绝缘体上形成第二绝缘体。通孔形成在第二绝缘体中，并通过通孔与第一导体电耦合。第二导体形成在第二绝缘体上，并且通过通孔与第一导体电耦合。第二导体被图案化。在第二导体下面形成空腔，在第一和第二绝缘体中形成空腔。

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