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21. 发明申请

US20090286375A1 METHOD OF FORMING SIDEWALL SPACERS TO REDUCE FORMATION OF RECESSES IN THE SUBSTRATE AND INCREASE DOPANT RETENTION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：形成侧壁间隔的方法，以减少在基底中形成的凹陷并增加半导体器件中的氘保持
公开(公告)号：US20090286375A1
公开(公告)日：2009-11-19
申请号：US12122885
申请日：2008-05-19
申请人： Mahalingam Nandakumar , Said Ghneim , Frank Scott Johnson
发明人： Mahalingam Nandakumar , Said Ghneim , Frank Scott Johnson
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L29/6656
摘要： A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer.
摘要翻译：在半导体器件中形成用于栅极的侧壁间隔物的方法包括：在栅极形成之后，再次氧化/退火衬底的硅和栅极的硅。通过在惰性气氛或环境中进行退火，使基板再次氧化。在沉积覆盖衬底和栅极的氧化物层之后，衬底可以被再氧化/退火。此外，可以在形成栅极之后再次氧化/退火衬底，而不沉积氧化物层。

22. 发明申请

US20070287274A1 Implantation of carbon and/or fluorine in NMOS fabrication 有权
标题翻译：在NMOS制造中植入碳和/或氟
公开(公告)号：US20070287274A1
公开(公告)日：2007-12-13
申请号：US11451919
申请日：2006-06-13
申请人： Mahalingam Nandakumar , Amitabh Jain , Lahir Shaik Adam
发明人： Mahalingam Nandakumar , Amitabh Jain , Lahir Shaik Adam
IPC分类号： H01L21/425
CPC分类号： H01L21/2658 , H01L21/26506 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.
摘要翻译：公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F 2 O 2）中的至少一种与砷，磷和锑中的至少一种的注入相结合。掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

23. 发明授权

US06960499B2 Dual-counterdoped channel field effect transistor and method 有权
标题翻译：双对流通道场效应晶体管及方法
公开(公告)号：US06960499B2
公开(公告)日：2005-11-01
申请号：US10866469
申请日：2004-06-14
申请人： Mahalingam Nandakumar , Karthik Vasanth , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Karthik Vasanth , Ih-Chin Chen
IPC分类号： H01L21/265 , H01L29/10 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/1033
摘要： A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.
摘要翻译：公开了一种具有双重反向通道的场效应晶体管。晶体管具有包括第一掺杂区域（28）和位于第一掺杂区域下方的第二掺杂区域（26）的沟道。源极和漏极（32）形成在与沟道相邻的位置。在本发明的一个实施例中，第一掺杂区域（28）掺杂有砷，而第二掺杂区域（26）掺杂有磷。地下通道层（28）的高电荷载流子迁移率允许使用较低的沟道掺杂剂浓度，这又允许较低的源极/漏极口袋掺杂。这降低了晶体管的电容和响应时间。

24. 发明授权

US06882013B2 Transistor with reduced short channel effects and method 有权
公开(公告)号：US06882013B2
公开(公告)日：2005-04-19
申请号：US10355675
申请日：2003-01-30
申请人： Mahalingam Nandakumar
发明人： Mahalingam Nandakumar
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6653 , H01L29/66492 , H01L29/6656 , H01L29/6659
摘要： A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43).

25. 发明授权

US06713334B2 Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask 有权
标题翻译：在高电压屏蔽下，使用额外的注入芯片制造双电压CMOSFET
公开(公告)号：US06713334B2
公开(公告)日：2004-03-30
申请号：US10215925
申请日：2002-08-09
申请人： Mahalingam Nandakumar , Youngmin Kim , Amitava Chatterjee
发明人： Mahalingam Nandakumar , Youngmin Kim , Amitava Chatterjee
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/823857
摘要： An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.
摘要翻译：提供HVGX模式的植入（步骤102c）以允许在核心晶体管上选择性晶体管阈值电压Vth调节，而不影响I / O晶体管阈值电压Vt。注入提供独立调谐的NMOS核心晶体管和I / O晶体管Vth或 PMOS晶体管和I / O晶体管Vth。

26. 发明授权

US06326281B1 Integrated circuit isolation 有权
标题翻译：集成电路隔离
公开(公告)号：US06326281B1
公开(公告)日：2001-12-04
申请号：US09405278
申请日：1999-09-23
申请人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
发明人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
IPC分类号： H01L2136
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/31604 , H01L21/762
摘要： Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.
摘要翻译：通过在氧化硅（201）上由氮化硅（202）制成的掩模中的硅通过窗口外延生长硅氧化硅衬底，氧化硅被蚀刻以切割氮化硅; 掩模在硅衬底上。

27. 发明授权

US06306712B1 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing 有权
标题翻译：改善CMOS的侧壁工艺和植入方法，有利于低CGD，改善掺杂特性和对化学处理的不敏感性
公开(公告)号：US06306712B1
公开(公告)日：2001-10-23
申请号：US09205637
申请日：1998-12-03
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/26586 , H01L29/0847 , H01L29/1083 , H01L29/4983 , H01L29/66545 , H01L29/6656 , H01L29/66628 , Y10S438/926 , Y10S438/931
摘要： A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).
摘要翻译：本文公开了一种用于使用边缘阻挡材料（24）形成晶体管的晶体管（30）和方法。边缘阻挡材料（24）可以位于邻近门（22）或一次性门，或者可以是一次性门的一部分。在成角度的袋式注入期间，边缘阻挡材料（24）阻挡一些掺杂剂进入半导体本体（10），并且位于边缘阻挡材料下面的掺杂剂（18）位于半导体本体表面下方给定的距离处 10）。

28. 发明授权

US5976937A Transistor having ultrashallow source and drain junctions with reduced gate overlap and method 有权
标题翻译：具有超低源极和漏极结的晶体管具有减少的栅极重叠和方法
公开(公告)号：US5976937A
公开(公告)日：1999-11-02
申请号：US136750
申请日：1998-08-19
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/1083 , H01L21/26586 , H01L21/823418 , H01L29/66492 , H01L29/6659
摘要： Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126). The dopants are implanted in the first direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (166 and 168) of the second active area (142). Dopants may be implanted from a second direction substantially parallel to the second gate electrode (140) and perpendicular to the first direction into the source and drain sections (166 and 168) of the second active area (142). The dopants are implanted in the second direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (162 and 164) of the first active area (126).
摘要翻译：制造具有减少的栅极重叠的超短源极和漏极结的晶体管的方法可以包括通过第一栅极绝缘体（130）形成与半导体层（112）的第一有源区（126）分离的第一栅电极（124）。第二栅极电极（140）可以形成为基本上垂直于第一栅电极（124）并且通过第二栅极绝缘体（146）与半导体层的第二有源区域（142）分离。可以在半导体层（112）之上形成掩模层（160）并且暴露第一有源区域（126）的源极和漏极部分（162和164）以及源极和漏极部分（166和168）第二活动区域（142）。掺杂剂可以从基本上平行于第一栅电极（124）的第一方向注入到第一有源区（126）的源区和漏区（166和168）中。所述掺杂剂以所述掩蔽层（160）阻止所述掺杂剂进入所述第二有源区域（142）的源极和漏极部分（166和168）的角度沿所述第一方向植入。掺杂剂可以从基本上平行于第二栅电极（140）并垂直于第一方向的第二方向注入第二有源区（142）的源区和漏区（166和168）中。所述掺杂剂以所述掩蔽层（160）阻挡所述掺杂剂进入所述第一有源区（126）的源区和漏区（162和164）的角度在第二方向上注入。

29. 发明授权

US5917219A Semiconductor devices with pocket implant and counter doping 失效
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US5917219A
公开(公告)日：1999-06-29
申请号：US725599
申请日：1996-10-03
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L27/01 , H01L27/12 , H01L31/0397
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

30. 发明授权

US5296725A Integrated multicelled semiconductor switching device for high current applications 失效
标题翻译：用于高电流应用的集成多标准半导体开关器件
公开(公告)号：US5296725A
公开(公告)日：1994-03-22
申请号：US896656
申请日：1992-06-10
申请人： Mahalingam Nandakumar , Bantval J. Baliga
发明人： Mahalingam Nandakumar , Bantval J. Baliga
IPC分类号： H01L29/749 , H01L31/111 , H01L29/74
CPC分类号： H01L29/749
摘要： An integrated multicelled thyristor includes a plurality of main thyristor cells and a plurality of edge thyristor cells. The main thyristor cells comprise source cells located in the center or innermost portion of an integrated thyristor and the edge cells are located at the periphery. In order to insure that all thyristor cells turn off uniformly, current exporting means is provided from the source cells to the edge cells to reduce current hole crowding in the peripheral cells. The anodes of all cells are electrically connected and the cathodes of all main cells are electrically connected. However, the cathodes of the edge cells are electrically connected to one or more source cells by the current exporting means. The unit cell of the multicelled device preferably comprises a BRT, but can comprise other well known thyristor structures where turn-off is limited by hole-current crowding.
摘要翻译：集成多级晶闸管包括多个主晶闸管单元和多个边缘晶闸管单元。主晶闸管电池包括位于集成晶闸管的中心或最内部的源电池，并且边缘电池位于外围。为了确保所有晶闸管电池均匀关断，从源电池向边缘电池提供电流输出装置，以减少外围电池中的电流孔挤塞。所有电池的阳极电连接，并且所有主电池的阴极电连接。然而，边缘电池的阴极通过电流输出装置电连接到一个或多个源电池。多标记器件的晶胞优选地包括BRT，但是可以包括其他公知的晶闸管结构，其中关断由空穴电流拥挤限制。

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