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1. 发明授权

US06228725B1 Semiconductor devices with pocket implant and counter doping 有权
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US06228725B1
公开(公告)日：2001-05-08
申请号：US09281543
申请日：1999-03-30
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

2. 发明授权

US06258644B1 Mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps 有权
标题翻译：混合电压CMOS工艺，用于高可靠性和高性能的核心和I / O晶体管，减少了掩模步骤
公开(公告)号：US06258644B1
公开(公告)日：2001-07-10
申请号：US09499719
申请日：2000-02-08
申请人： Mark S. Rodder , Manoj Mehrotra , Mahalingam Nandakumar
发明人： Mark S. Rodder , Manoj Mehrotra , Mahalingam Nandakumar
IPC分类号： H01L218238
CPC分类号： H01L21/823814
摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.
摘要翻译：用于高可靠性和高性能核心晶体管和输入输出晶体管的混合电压CMOS工艺，减少了掩模步骤。在硅衬底（10）上形成栅叠层（30）。对第一种和第二种进行离子注入，以在输入输出晶体管中产生掺杂分布（70,80,90,100）。

3. 发明授权

US06306712B1 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing 有权
标题翻译：改善CMOS的侧壁工艺和植入方法，有利于低CGD，改善掺杂特性和对化学处理的不敏感性
公开(公告)号：US06306712B1
公开(公告)日：2001-10-23
申请号：US09205637
申请日：1998-12-03
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/26586 , H01L29/0847 , H01L29/1083 , H01L29/4983 , H01L29/66545 , H01L29/6656 , H01L29/66628 , Y10S438/926 , Y10S438/931
摘要： A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).
摘要翻译：本文公开了一种用于使用边缘阻挡材料（24）形成晶体管的晶体管（30）和方法。边缘阻挡材料（24）可以位于邻近门（22）或一次性门，或者可以是一次性门的一部分。在成角度的袋式注入期间，边缘阻挡材料（24）阻挡一些掺杂剂进入半导体本体（10），并且位于边缘阻挡材料下面的掺杂剂（18）位于半导体本体表面下方给定的距离处 10）。

4. 发明授权

US5976937A Transistor having ultrashallow source and drain junctions with reduced gate overlap and method 有权
标题翻译：具有超低源极和漏极结的晶体管具有减少的栅极重叠和方法
公开(公告)号：US5976937A
公开(公告)日：1999-11-02
申请号：US136750
申请日：1998-08-19
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/1083 , H01L21/26586 , H01L21/823418 , H01L29/66492 , H01L29/6659
摘要： Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126). The dopants are implanted in the first direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (166 and 168) of the second active area (142). Dopants may be implanted from a second direction substantially parallel to the second gate electrode (140) and perpendicular to the first direction into the source and drain sections (166 and 168) of the second active area (142). The dopants are implanted in the second direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (162 and 164) of the first active area (126).
摘要翻译：制造具有减少的栅极重叠的超短源极和漏极结的晶体管的方法可以包括通过第一栅极绝缘体（130）形成与半导体层（112）的第一有源区（126）分离的第一栅电极（124）。第二栅极电极（140）可以形成为基本上垂直于第一栅电极（124）并且通过第二栅极绝缘体（146）与半导体层的第二有源区域（142）分离。可以在半导体层（112）之上形成掩模层（160）并且暴露第一有源区域（126）的源极和漏极部分（162和164）以及源极和漏极部分（166和168）第二活动区域（142）。掺杂剂可以从基本上平行于第一栅电极（124）的第一方向注入到第一有源区（126）的源区和漏区（166和168）中。所述掺杂剂以所述掩蔽层（160）阻止所述掺杂剂进入所述第二有源区域（142）的源极和漏极部分（166和168）的角度沿所述第一方向植入。掺杂剂可以从基本上平行于第二栅电极（140）并垂直于第一方向的第二方向注入第二有源区（142）的源区和漏区（166和168）中。所述掺杂剂以所述掩蔽层（160）阻挡所述掺杂剂进入所述第一有源区（126）的源区和漏区（162和164）的角度在第二方向上注入。

5. 发明授权

US5917219A Semiconductor devices with pocket implant and counter doping 失效
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US5917219A
公开(公告)日：1999-06-29
申请号：US725599
申请日：1996-10-03
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L27/01 , H01L27/12 , H01L31/0397
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

6. 发明授权

US06579770B2 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing 有权
标题翻译：改善CMOS的侧壁工艺和植入方法，有利于低CGD，改善掺杂特性和对化学处理的不敏感性
公开(公告)号：US06579770B2
公开(公告)日：2003-06-17
申请号：US09899783
申请日：2001-07-05
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/26586 , H01L29/0847 , H01L29/1083 , H01L29/4983 , H01L29/66545 , H01L29/6656 , H01L29/66628 , Y10S438/926 , Y10S438/931
摘要： A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).
摘要翻译：本文公开了一种用于使用边缘阻挡材料（24）形成晶体管的晶体管（30）和方法。边缘阻挡材料（24）可以位于邻近门（22）或一次性门，或者可以是一次性门的一部分。在成角度的袋式注入期间，边缘阻挡材料（24）阻挡一些掺杂剂进入半导体本体（10），并且位于边缘阻挡材料下面的掺杂剂（18）位于半导体本体表面下方给定的距离处 10）。

7. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

8. 发明申请

US20090166675A1 STRAIN ENGINEERING IN SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体器件中的应变工程
公开(公告)号：US20090166675A1
公开(公告)日：2009-07-02
申请号：US12346458
申请日：2008-12-30
申请人： Mahalingam Nandakumar
发明人： Mahalingam Nandakumar
IPC分类号： H01L29/737 , H01L21/265 , H01L21/337
CPC分类号： H01L21/02658 , H01L21/02667
摘要： This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.
摘要翻译：本公开涉及应变工程，以改善包括半导体衬底的应变区域的半导体部件的性能。本公开涉及目标区域的非晶化和原子格子的再结晶，同时在该区域上施加应变。这样形成的区域将形成应变格子，其中应变均匀地分布在整个区域中，并且即使去除了机械应变源，其也保留了本征应变。本公开包括用于形成具有应变区域（例如具有应变通道区域的半导体部件）和由其形成的半导体部件的半导体衬底的方法以及具有各种性质和优点的变型。

9. 发明申请

US20090004805A1 Damage Implantation of a Cap Layer 有权
标题翻译：盖层的损伤植入
公开(公告)号：US20090004805A1
公开(公告)日：2009-01-01
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L23/58
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

10. 发明授权

US07393787B2 Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment 有权
标题翻译：使用高温化学处理形成其中具有均匀氮分布的含氮介电层
公开(公告)号：US07393787B2
公开(公告)日：2008-07-01
申请号：US11209140
申请日：2005-08-22
申请人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
发明人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
IPC分类号： H01L21/302
CPC分类号： H01L27/11 , H01L21/823462 , H01L21/823857 , H01L21/8249
摘要： The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric layer (520) having a non-uniformity of nitrogen in a bulk thereof, and removing at least a portion of the nitrided dielectric layer (520) using a high temperature chemical treatment, the removing reducing the non-uniformity.
摘要翻译：本发明提供一种栅极电介质的制造方法，半导体器件的制造方法以及集成电路的制造方法。用于制造栅极电介质的方法，但不限于，可以包括在衬底（310）上形成氮化介电层（520），氮化介电层（520）在其主体中具有不均匀的氮，并且在使用高温化学处理的氮化介电层（520）的至少一部分，去除减少不均匀性。

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