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1. 发明授权

US08846487B2 Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology 有权
标题翻译：使用DSB基板和热技术在半导体器件制造过程中减少SPE中的角部缺陷
公开(公告)号：US08846487B2
公开(公告)日：2014-09-30
申请号：US13544519
申请日：2012-07-09
申请人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
发明人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/84 , H01L21/762 , H01L29/04
CPC分类号： H01L21/76275 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045
摘要： A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
摘要翻译：一种降低混合取向晶体管中的残留STI拐角缺陷的装置和方法，包括：形成直接硅键合衬底，其中具有第二晶体取向的第二硅层以第一晶体取向结合到手柄衬底上，形成衬垫氧化物层在所述第二硅层上，在所述焊盘氧化物层上形成氮化物层，通过所述第二硅层在所述直接硅键合衬底内形成隔离沟槽并进入所述处理衬底，使用光致抗蚀剂构图所述直接硅键合衬底的PMOS区域隔离沟槽的一部分，将直接硅键合衬底的NMOS区域注入和非晶化，去除光致抗蚀剂，进行固相外延，进行再结晶退火，形成STI衬垫，完成前端处理和执行后端处理。

2. 发明授权

US08828835B2 Ultrashallow emitter formation using ALD and high temperature short time annealing 有权
标题翻译：使用ALD和高温短时退火的超疏水发射体形成
公开(公告)号：US08828835B2
公开(公告)日：2014-09-09
申请号：US12718142
申请日：2010-03-05
申请人： Rick L. Wise , Hiroshi Yasuda
发明人： Rick L. Wise , Hiroshi Yasuda
IPC分类号： H01L21/331 , H01L21/02 , H01L29/732 , H01L21/225 , H01L29/66
CPC分类号： H01L29/36 , H01L21/02063 , H01L21/2254 , H01L29/66242 , H01L29/66272 , H01L29/73 , H01L29/7325
摘要： An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
摘要翻译：一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

3. 发明申请

US20080308847A1 METHOD OF MAKING (100) NMOS AND (110) PMOS SIDEWALL SURFACE ON THE SAME FIN ORIENTATION FOR MULTIPLE GATE MOSFET WITH DSB SUBSTRATE 有权
标题翻译：在具有DSB基板的多个栅极MOSFET的同一熔接方向上制造（100）NMOS和（110）PMOS面板表面的方法
公开(公告)号：US20080308847A1
公开(公告)日：2008-12-18
申请号：US11764442
申请日：2007-06-18
申请人： Weize XIONG , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize XIONG , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0° and 90° to the PMOS fin and includes a second surface of a second crystal orientation.
摘要翻译：公开了一种形成包括多个MuGFET的集成电路器件的方法。在基板上形成MuGFET的PMOS鳍。 PMOS鳍包括第一晶体取向的第一表面的沟道。在基板上形成另一个MuGFET的NMOS鳍。所述NMOS鳍片包括在所述衬底上与所述PMOS鳍片0°和90°之一处的通道，并且包括第二晶体取向的第二表面。

4. 发明申请

US20080185675A1 Trench Isolation Structure and a Method of Manufacture Therefor 审中-公开
标题翻译：沟槽隔离结构及其制造方法
公开(公告)号：US20080185675A1
公开(公告)日：2008-08-07
申请号：US12101965
申请日：2008-04-12
申请人： Rick L. Wise , Mark S. Rodder
发明人： Rick L. Wise , Mark S. Rodder
IPC分类号： H01L23/58
CPC分类号： H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.
摘要翻译：本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁上的缓冲层（133）。沟槽隔离结构（130）还包括位于缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

5. 发明授权

US06496352B2 Post-in-crown capacitor and method of manufacture 有权
标题翻译：后置电容器及其制造方法
公开(公告)号：US06496352B2
公开(公告)日：2002-12-17
申请号：US09335348
申请日：1999-06-17
申请人： Darius L. Crenshaw , William F. Richardson , Rick L. Wise
发明人： Darius L. Crenshaw , William F. Richardson , Rick L. Wise
IPC分类号： H01G4005
CPC分类号： H01L28/91 , H01L21/3212 , H01L28/84
摘要： A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).
摘要翻译：公开了一种后置电容器。冠状后电容器（60）包括联接到导电通路（20）的表冠（44）。柱（48）设置在表冠（44）内，并且从表冠（44）和柱（48）向外形成电容器绝缘层（50）。然后从电容器绝缘层（50）向外形成电容器板层（52）。

6. 发明授权

US6135460A Method of and apparatus for purifying reduced pressure process chambers 失效
标题翻译：减压处理室的净化方法及装置
公开(公告)号：US6135460A
公开(公告)日：2000-10-24
申请号：US124799
申请日：1998-07-29
申请人： Rick L. Wise , Michael A. Kasner
发明人： Rick L. Wise , Michael A. Kasner
IPC分类号： B01D53/04 , C09K3/10 , H01L21/00
CPC分类号： H01L21/67017 , B01D53/04 , C09K3/10 , B01D2253/202 , B01D2258/0216 , Y10S277/913 , Y10S277/918
摘要： Gas purification resins are encapsulated in deformable, permeable polymer sheaths to form purification rings, gaskets or seals. A primary source of contaminants in advanced vacuum processors equipped with vacuum load-lock systems and process gas purifiers is from the leakage of outside ambient contaminants around O-ring seals. Using gas purification rings, gaskets or seals properly placed inside or outside of the outer O-ring seal, the level of contaminants (particularly hydrocarbons, oxygen and moisture) may be significantly reduced or eliminated. The gas purification ring is preferably a hydrocarbon and/or oxygen and/or moisture absorbing and/or adsorbing material encased within a contaminant permeable casing. The gas purification ring can be round or flattened and is preferably more resilient than the O-rings adjacent thereto which form the seal. An adhesive can be placed around the casing holding the purification resin to prevent movement from its purifying location.
摘要翻译：气体净化树脂被封装在可变形的可渗透的聚合物护套中以形成净化环，垫圈或密封件。配备真空负载锁定系统和工艺气体净化器的先进真空处理器中的主要污染源是O型圈密封件周围外部污染物的泄漏。使用气体净化环，垫圈或密封圈适当地放置在外部O形圈密封件的内部或外部，污染物（特别是碳氢化合物，氧气和水分）的水平可能会显着降低或消除。气体净化环优选为包封在可渗透污染的外壳内的烃类和/或氧气和/或吸湿材料和/或吸附材料。气体净化环可以是圆形或扁平的，并且优选地比形成密封件的与其相邻的O形环更有弹性。粘合剂可以放置在保持净化树脂的外壳周围，以防止从其净化位置移动。

7. 发明申请

US20140045321A1 ACCELERATED FURNACE RAMP RATES FOR REDUCED SLIP 有权
标题翻译：加速冷却速率降低
公开(公告)号：US20140045321A1
公开(公告)日：2014-02-13
申请号：US13584004
申请日：2012-08-13
申请人： Bradley David SUCHER , Rick L. WISE
发明人： Bradley David SUCHER , Rick L. WISE
IPC分类号： H01L21/20
CPC分类号： H01L21/02238 , H01L21/3225 , H01L21/324
摘要： A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (≧) 5.5° C./min.
摘要翻译：集成电路（IC）的制造方法包括基板的半导体表面的初始氧化。在初始氧化之后，使用多个炉子加工步骤对基板进行加热，炉子加工步骤各自包括800℃和1300℃之间的峰值处理温度。炉子加工步骤包括至少一个加速加工步骤，该加工步骤在温度范围在800°C至1250°C之间，提供加速斜坡上升速率和/或加速斜坡下降速率至少（> =）5.5℃/分钟。

8. 发明申请

US20120175710A1 INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS 有权
标题翻译：具有对准（100）NMOS和（110）PMOS FinFET平台通道的集成电路
公开(公告)号：US20120175710A1
公开(公告)日：2012-07-12
申请号：US13425082
申请日：2012-03-20
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L27/092
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
摘要翻译：公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

9. 发明申请

US20110057289A1 Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing 有权
标题翻译：使用ALD和高温短时退火的超短发射体形成
公开(公告)号：US20110057289A1
公开(公告)日：2011-03-10
申请号：US12718142
申请日：2010-03-05
申请人： Rick L. Wise , Hiroshi Yasuda
发明人： Rick L. Wise , Hiroshi Yasuda
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/36 , H01L21/02063 , H01L21/2254 , H01L29/66242 , H01L29/66272 , H01L29/73 , H01L29/7325
摘要： An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
摘要翻译：一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

10. 发明授权

US08410519B2 Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels 有权
标题翻译：具有对准（100）NMOS和（110）PMOS FinFET侧壁通道的集成电路
公开(公告)号：US08410519B2
公开(公告)日：2013-04-02
申请号：US13425082
申请日：2012-03-20
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L29/66
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
摘要翻译：公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

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