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1. 发明授权

US06713334B2 Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask 有权
标题翻译：在高电压屏蔽下，使用额外的注入芯片制造双电压CMOSFET
公开(公告)号：US06713334B2
公开(公告)日：2004-03-30
申请号：US10215925
申请日：2002-08-09
申请人： Mahalingam Nandakumar , Youngmin Kim , Amitava Chatterjee
发明人： Mahalingam Nandakumar , Youngmin Kim , Amitava Chatterjee
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/823857
摘要： An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.
摘要翻译：提供HVGX模式的植入（步骤102c）以允许在核心晶体管上选择性晶体管阈值电压Vth调节，而不影响I / O晶体管阈值电压Vt。注入提供独立调谐的NMOS核心晶体管和I / O晶体管Vth或 PMOS晶体管和I / O晶体管Vth。

2. 发明授权

US06822297B2 Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness 有权
标题翻译：额外的n型LDD /袋式注入，用于改善短沟道NMOS ESD稳健性
公开(公告)号：US06822297B2
公开(公告)日：2004-11-23
申请号：US09876292
申请日：2001-06-07
申请人： Mahalingam Nandakumar , Song Zhao , Youngmin Kim
发明人： Mahalingam Nandakumar , Song Zhao , Youngmin Kim
IPC分类号： H01L2362
CPC分类号： H01L29/6659 , H01L27/0266 , H01L29/1083 , H01L29/7833
摘要： A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions. According to the invention, these regions of higher p-type resistivity are created after gate definition by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants creating the extended source and drain and the pockets of enhanced p-doping. In an ESD event, these regions of higher resistivity increase the current gain of the parasitic lateral npn bipolar transistor and thus raise the current It2, which initiates the thermal breakdown with its destructive localized heating, thereby improving ESD robustness.
摘要翻译： p阱中的短沟道NMOS晶体管具有n源极和n沟道，每个包含延伸到晶体管栅极的浅区域，每个侧面由隔离区域横向限定并由沟道停止区域垂直地限定以及从栅极凹陷的较深区域，并且当反向偏置时都具有耗尽区域。浅区域部分地被增强的p掺杂注入口袋包围。晶体管还在这些增强的p掺杂区域中具有比半导体其余部分高的p电阻率的另一区域。这些区域大致从相应的浅区域的内部边界横向延伸到相应的凹陷区域的内部边界，并且从刚好在源极和漏极的耗尽区域的深度的深度垂直地延伸到接近通道停止区域的顶部。根据本发明通过使用已经用于形成扩展的源极和漏极的植入物的相同的光掩模，通过补偿n掺杂的离子注入（例如砷或磷）在栅极定义之后产生这些较高p型电阻率的区域，在ESD事件中，这些具有较高电阻率的区域增加了寄生横向npn双极晶体管的电流增益，从而提高了电流It2，从而使其具有破坏性的局部加热引起热击穿，从而提高了ESD鲁棒性。

3. 发明授权

US06730555B2 Transistors having selectively doped channel regions 有权
标题翻译：具有选择性掺杂沟道区的晶体管
公开(公告)号：US06730555B2
公开(公告)日：2004-05-04
申请号：US10153033
申请日：2002-05-22
申请人： Youngmin Kim , Amitava Chatterjee
发明人： Youngmin Kim , Amitava Chatterjee
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： An integrated semiconductor system is provided that is formed on a substrate 10. A dual implant mask 26 is used to change the characteristics of semiconductor devices formed in regions of the substrate 10 having different characteristics. Transistors 50 and 52 can be formed on the same substrate 10 and have different electrical characteristics.
摘要翻译：提供了形成在基板10上的集成半导体系统。双注入掩模26用于改变在具有不同特性的基板10的区域中形成的半导体器件的特性。晶体管50和52可以形成在相同的基板10上并且具有不同的电特性。

4. 发明授权

US06794730B2 High performance PNP bipolar device fully compatible with CMOS process 有权
标题翻译：高性能PNP双极器件完全兼容CMOS工艺
公开(公告)号：US06794730B2
公开(公告)日：2004-09-21
申请号：US10028002
申请日：2001-12-20
申请人： Youngmin Kim , Shaoping Tang , Seetharaman Sridhar , Amitava Chatterjee
发明人： Youngmin Kim , Shaoping Tang , Seetharaman Sridhar , Amitava Chatterjee
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.
摘要翻译：通过减小p阱注入的深度以增加发射极中的载流子浓度并使发射极结更深以增加发射极中的少数寿命，形成pnp双极结型晶体管，其具有改善的发射极效率。形成高增益BJT，而不对工艺流程添加掩模步骤。在优选实施例中，使用覆盖的高能量硼注入来抑制SRAM中的隔离泄漏。

5. 发明授权

US06767810B2 Method to increase substrate potential in MOS transistors used in ESD protection circuits 有权
标题翻译：在ESD保护电路中使用的MOS晶体管中增加衬底电位的方法
公开(公告)号：US06767810B2
公开(公告)日：2004-07-27
申请号：US10629514
申请日：2003-07-29
申请人： Craig T. Salling , Amitava Chatterjee , Youngmin Kim
发明人： Craig T. Salling , Amitava Chatterjee , Youngmin Kim
IPC分类号： H01L218249
CPC分类号： H01L27/0277
摘要： An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad. In the first embodiment, the space includes a dummy gate; in the second embodiment, an isolation region; in the third embodiment, the space a protected, stable surface.
摘要翻译：位于半导体芯片表面的隔离沟槽之间的集成电路，包括具有第一电阻率的第一导电类型的第一阱。该第一阱具有比第一电阻率更高的电阻率的浅埋入区，在隔离沟槽之间延伸并由补偿掺杂工艺产生。电路还包括延伸到隔离沟槽之间的表面的相反导电类型的第二阱，具有接触区域并与第一阱的浅埋入区域基本上平行于表面形成结。最后，电路具有位于第二阱中的MOS晶体管，与接触区域间隔开，并且在表面具有源极，栅极和漏极区域。该空间是预定的，以在I / O晶体管中产生一个小的电压降，用于调节信号和对焊盘的功率，或者ESD电路中的大的电压降，用于保护连接到焊盘的有源电路。在第一实施例中，空间包括虚拟门; 在第二实施例中，隔离区域; 在第三实施例中，空间是受保护的，稳定的表面。

6. 发明授权

US06514810B1 Buried channel PMOS transistor in dual gate CMOS with reduced masking steps 有权
标题翻译：双栅极CMOS中的掩埋沟道PMOS晶体管，具有减小的掩模步骤
公开(公告)号：US06514810B1
公开(公告)日：2003-02-04
申请号：US09920157
申请日：2001-08-01
申请人： Youngmin Kim , Amitava Chatterjee
发明人： Youngmin Kim , Amitava Chatterjee
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L21/823807
摘要： A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.
摘要翻译：用于模拟应用的掩埋沟道PMOS晶体管被集成到数字CMOS工艺中。通过在半导体衬底中注入所有n型和p型衬底以形成用于数字CMOS工艺的n阱和p阱区域的区域来形成第三阱区（105）。栅电介质层（50）和栅极层（109）形成在第三阱（105）的上方并且包括掩埋沟道PMOS晶体管的栅叠层。用于形成漏极延伸区域和CMOS晶体管的源极和漏极区域的注入用于完成掩埋沟道PMOS晶体管。

7. 发明授权

US10081898B2 Laundry apparatus 有权
公开(公告)号：US10081898B2
公开(公告)日：2018-09-25
申请号：US13097934
申请日：2011-04-29
申请人： Sungryong Kim , Dongwon Kim , Kyeonghwan Kim , Heakyung Yoo , Youngmin Kim
发明人： Sungryong Kim , Dongwon Kim , Kyeonghwan Kim , Heakyung Yoo , Youngmin Kim
IPC分类号： D06F29/00 , D06F29/02 , D06F39/08 , D06F39/12 , D06F39/10
CPC分类号： D06F29/02 , D06F29/00 , D06F39/08 , D06F39/085 , D06F39/10 , D06F39/12
摘要： A laundry apparatus including a cabinet; a first space provided in the cabinet, in which a first treating part provided to treat laundry is installed; a second space provided in the cabinet, in which a second treating part provided to treat laundry is installed; a drawer movably provided in the second space, in which the second treating part is installed; and a rail unit configured to limit vertical and horizontal movement of the drawer with respect to the second space and to guide the outward movement of the drawer. Therefore, laundry may be treated by using the first and second treating parts and vibration and noise generated in the second treating part may be reduced.

8. 发明授权

US07948676B2 Automated cassette and slide handling system for an automatic microscope 有权
标题翻译：自动显微镜自动盒式和滑动处理系统
公开(公告)号：US07948676B2
公开(公告)日：2011-05-24
申请号：US11833517
申请日：2007-08-03
申请人： Tibor Virag , Yash Agarwal , Wei Guo , Richard Eberle , Youngmin Kim , Michael Kilpatrick , Petros Tsipouras , Triantafyllos Tafas
发明人： Tibor Virag , Yash Agarwal , Wei Guo , Richard Eberle , Youngmin Kim , Michael Kilpatrick , Petros Tsipouras , Triantafyllos Tafas
IPC分类号： G02B21/26
CPC分类号： G02B21/34 , G01N35/026 , G01N35/04 , G01N2035/0425 , G01N2035/0427 , Y10S359/90
摘要： An automated cassette and slide handling system is disclosed which organizes microscope slides in cassettes, automatically and sequentially removes individual slides from their respective cassettes, positioned each slide under the microscope as provided by the protocol, and after examination returns the slide to its proper cassette.
摘要翻译：公开了一种自动化的盒式磁带和幻灯片处理系统，其在盒中组织显微镜幻灯片，自动地并且顺序地从其各自的盒中移除各个幻灯片，每个幻灯片根据协议设置在显微镜下放置，并且在检查后将幻灯片返回到其正确的盒。

9. 发明授权

US07901887B2 Automated cancer diagnostic methods using fish 有权
标题翻译：使用鱼的自动化癌症诊断方法
公开(公告)号：US07901887B2
公开(公告)日：2011-03-08
申请号：US12051032
申请日：2008-03-19
申请人： Triantafyllos P. Tafas , Michael Kilpatrick , Xiuzhong Wang , Youngmin Kim , Michael Thomas , Petros Tsipouras
发明人： Triantafyllos P. Tafas , Michael Kilpatrick , Xiuzhong Wang , Youngmin Kim , Michael Thomas , Petros Tsipouras
IPC分类号： C12Q1/68 , C07H21/04
CPC分类号： G01N33/5005 , G01N21/6458 , G01N2021/6439 , G06K9/0014 , G06T7/0012 , G06T2207/10056 , G06T2207/30024
摘要： In various embodiments methods for automated screening for gene amplification in biological tissue samples using an automated fluorescence microscope to analyze fluorescence in situ hybridized samples are provided. Various additional embodiments provide methods of high throughput screening for gene amplification.
摘要翻译：在各种实施方案中，提供了使用自动荧光显微镜自动筛选生物组织样品中基因扩增以分析荧光原位杂交样品的方法。各种另外的实施方案提供了用于基因扩增的高通量筛选方法。

10. 发明申请

US20090123054A1 DETECTION OF CIRCULATING TUMOR CELLS IN PERIPHERAL BLOOD WITH AN AUTOMATED SCANNING FLUORESCENCE MICROSCOPE 有权
标题翻译：用自动扫描荧光显微镜检测外周血中循环肿瘤细胞
公开(公告)号：US20090123054A1
公开(公告)日：2009-05-14
申请号：US12270820
申请日：2008-11-13
申请人： Sir Walter Bodmer , Triantafyllos Tafas , Michael Kilpatrick , Petros Tsipouras , Xiuzhong Wang , Youngmin Kim , Michael Thomas , Antti Seppo , Triantafyllia Ntouroupi , Changhua Yu , Charles Climer
发明人： Sir Walter Bodmer , Triantafyllos Tafas , Michael Kilpatrick , Petros Tsipouras , Xiuzhong Wang , Youngmin Kim , Michael Thomas , Antti Seppo , Triantafyllia Ntouroupi , Changhua Yu , Charles Climer
IPC分类号： G06K9/00
CPC分类号： G06K9/00127 , G01N21/6458
摘要： An automated, highly sensitive, specific and potentially quantitative detection method using an automated microscope for identifying and enumerating rare cancer cells in blood and other fluids.
摘要翻译：一种使用自动显微镜识别和列举血液和其他液体中稀有癌细胞的自动化，高灵敏度，特异性和潜在的定量检测方法。

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