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1. 发明授权

US5294816A Unit cell arrangement for emitter switched thyristor with base resistance control 失效
标题翻译：用于具有基极电阻控制的发射极开关晶闸管的单元电池布置
公开(公告)号：US5294816A
公开(公告)日：1994-03-15
申请号：US897456
申请日：1992-06-10
申请人： Mallikarjunaswamy S. Shekar , Mahalingam Nandakumar , Bantval J. Baliga
发明人： Mallikarjunaswamy S. Shekar , Mahalingam Nandakumar , Bantval J. Baliga
IPC分类号： H01L29/745 , H01L29/749 , H01L23/48 , H01L29/74 , H01L29/76
CPC分类号： H01L29/749 , H01L29/7455 , H01L2924/0002
摘要： An emitter switched thyristor with base resistance control for preventing parasitic latch-up includes a P-N-P-N main thyristor with an N.sup.+ floating emitter for MOS-gated controlled turn-on and a lateral P-channel MOSFET for shunting hole current in a second base region to a P.sup.+ diverting region electrically connected to the cathode. The P-channel MOSFET is enabled by the application of a negative gate voltage to form a P-type inversion layer between the second base region and the P.sup.+ diverter region, thus reducing the resistance between the cathode and the second base region and raising the holding current of the emitter switched thyristor to above the operating current level. The formation of an alternative current path to the cathode has the further effect of reducing the forward bias across the base-emitter junction of an adjacent parasitic thyristor to thereby prevent the sustained regenerative action of the parasitic thyristor.
摘要翻译：具有用于防止寄生闩锁的基极电阻控制的发射极开关晶闸管包括具有用于MOS门控控制导通的N +浮置发射极的PNPN主晶闸管和用于在第二基极区中的分流电流的侧向P沟道MOSFET P +转移区电连接到阴极。 P沟道MOSFET通过施加负栅极电压来使能，以在第二基极区域和P +转移区域之间形成P型反型层，从而减小阴极和第二基极区域之间的电阻并且提高保持发射极开关晶闸管的电流高于工作电流电平。形成到阴极的替代电流路径具有减小相邻寄生晶闸管的基极 - 发射极结两端的正向偏压的进一步的效果，从而防止寄生晶闸管的持续再生作用。

2. 发明授权

US5296725A Integrated multicelled semiconductor switching device for high current applications 失效
标题翻译：用于高电流应用的集成多标准半导体开关器件
公开(公告)号：US5296725A
公开(公告)日：1994-03-22
申请号：US896656
申请日：1992-06-10
申请人： Mahalingam Nandakumar , Bantval J. Baliga
发明人： Mahalingam Nandakumar , Bantval J. Baliga
IPC分类号： H01L29/749 , H01L31/111 , H01L29/74
CPC分类号： H01L29/749
摘要： An integrated multicelled thyristor includes a plurality of main thyristor cells and a plurality of edge thyristor cells. The main thyristor cells comprise source cells located in the center or innermost portion of an integrated thyristor and the edge cells are located at the periphery. In order to insure that all thyristor cells turn off uniformly, current exporting means is provided from the source cells to the edge cells to reduce current hole crowding in the peripheral cells. The anodes of all cells are electrically connected and the cathodes of all main cells are electrically connected. However, the cathodes of the edge cells are electrically connected to one or more source cells by the current exporting means. The unit cell of the multicelled device preferably comprises a BRT, but can comprise other well known thyristor structures where turn-off is limited by hole-current crowding.
摘要翻译：集成多级晶闸管包括多个主晶闸管单元和多个边缘晶闸管单元。主晶闸管电池包括位于集成晶闸管的中心或最内部的源电池，并且边缘电池位于外围。为了确保所有晶闸管电池均匀关断，从源电池向边缘电池提供电流输出装置，以减少外围电池中的电流孔挤塞。所有电池的阳极电连接，并且所有主电池的阴极电连接。然而，边缘电池的阴极通过电流输出装置电连接到一个或多个源电池。多标记器件的晶胞优选地包括BRT，但是可以包括其他公知的晶闸管结构，其中关断由空穴电流拥挤限制。

3. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

4. 发明申请

US20090166675A1 STRAIN ENGINEERING IN SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体器件中的应变工程
公开(公告)号：US20090166675A1
公开(公告)日：2009-07-02
申请号：US12346458
申请日：2008-12-30
申请人： Mahalingam Nandakumar
发明人： Mahalingam Nandakumar
IPC分类号： H01L29/737 , H01L21/265 , H01L21/337
CPC分类号： H01L21/02658 , H01L21/02667
摘要： This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.
摘要翻译：本公开涉及应变工程，以改善包括半导体衬底的应变区域的半导体部件的性能。本公开涉及目标区域的非晶化和原子格子的再结晶，同时在该区域上施加应变。这样形成的区域将形成应变格子，其中应变均匀地分布在整个区域中，并且即使去除了机械应变源，其也保留了本征应变。本公开包括用于形成具有应变区域（例如具有应变通道区域的半导体部件）和由其形成的半导体部件的半导体衬底的方法以及具有各种性质和优点的变型。

5. 发明申请

US20090004805A1 Damage Implantation of a Cap Layer 有权
标题翻译：盖层的损伤植入
公开(公告)号：US20090004805A1
公开(公告)日：2009-01-01
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L23/58
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

6. 发明授权

US07393787B2 Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment 有权
标题翻译：使用高温化学处理形成其中具有均匀氮分布的含氮介电层
公开(公告)号：US07393787B2
公开(公告)日：2008-07-01
申请号：US11209140
申请日：2005-08-22
申请人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
发明人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
IPC分类号： H01L21/302
CPC分类号： H01L27/11 , H01L21/823462 , H01L21/823857 , H01L21/8249
摘要： The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric layer (520) having a non-uniformity of nitrogen in a bulk thereof, and removing at least a portion of the nitrided dielectric layer (520) using a high temperature chemical treatment, the removing reducing the non-uniformity.
摘要翻译：本发明提供一种栅极电介质的制造方法，半导体器件的制造方法以及集成电路的制造方法。用于制造栅极电介质的方法，但不限于，可以包括在衬底（310）上形成氮化介电层（520），氮化介电层（520）在其主体中具有不均匀的氮，并且在使用高温化学处理的氮化介电层（520）的至少一部分，去除减少不均匀性。

7. 发明授权

US06228725B1 Semiconductor devices with pocket implant and counter doping 有权
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US06228725B1
公开(公告)日：2001-05-08
申请号：US09281543
申请日：1999-03-30
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

8. 发明授权

US07678637B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US07678637B2
公开(公告)日：2010-03-16
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

9. 发明授权

US07638402B2 Sidewall spacer pullback scheme 有权
标题翻译：侧壁间隔回拉方案
公开(公告)号：US07638402B2
公开(公告)日：2009-12-29
申请号：US11728928
申请日：2007-03-27
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
IPC分类号： H01L21/336
CPC分类号： H01L21/823468 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.
摘要翻译：在形成晶体管时实现侧壁间隔器回拉方案。除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。

10. 发明申请

US20090170277A1 IMPLANT DAMAGE OF LAYER FOR EASY REMOVAL AND REDUCED SILICON RECESS 有权
标题翻译：对于易于去除和减少的硅损伤的层的损伤
公开(公告)号：US20090170277A1
公开(公告)日：2009-07-02
申请号：US12345414
申请日：2008-12-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/764 , H01L21/302
CPC分类号： H01L21/76254 , H01L21/3086 , H01L21/31111 , H01L21/32139
摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
摘要翻译：提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

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