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1. 发明授权

US09552997B2 Silicon carbide switching devices including P-type channels 有权
标题翻译：碳化硅切换装置包括P型通道
公开(公告)号：US09552997B2
公开(公告)日：2017-01-24
申请号：US13019723
申请日：2011-02-02
申请人： Mrinal Kanti Das , Qingchun Zhang , Sei-Hyung Ryu
发明人： Mrinal Kanti Das , Qingchun Zhang , Sei-Hyung Ryu
IPC分类号： H01L21/02 , H01L29/02 , H01L29/10 , H01L29/66 , H01L29/78 , H01L21/324 , H01L21/04 , H01L29/16 , H01L29/739 , H01L29/04
CPC分类号： H01L21/324 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7838 , Y10S438/931
摘要： Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1016 cm−3 to about 5×1018 cm−3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm2/V-s at a gate voltage of −25V.
摘要翻译：在碳化硅中形成p沟道MOS器件的方法包括在碳化硅层中形成n型阱，以及注入p型掺杂离子以在n型阱的表面形成p型区域并且在邻近p型区域的n型阱中至少部分地限定沟道区。在通道区域中形成阈值调整区域。注入的离子在惰性气氛中在大于1650℃的温度下进行退火。在沟道区上形成栅极氧化层，栅极氧化层上形成栅极。基于碳化硅的晶体管包括碳化硅层，碳化硅层中的n型阱以及在碳化硅层的表面处的n型阱中的p型区域，并且至少部分地限定沟道邻近p型区域的n型阱区域。阈值调整区域在通道区域中，并且包括掺杂剂浓度为约1×10 16 cm -3至约5×10 18 cm -3的p型掺杂剂。晶体管还包括在沟道区上的栅极氧化层和栅极氧化物层上的栅极。晶体管可以在-25V的栅极电压下在沟道区中表现出超过5cm 2 / V-s的空穴迁移率。

2. 发明授权

US09054022B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09054022B2
公开(公告)日：2015-06-09
申请号：US13579815
申请日：2011-07-29
申请人： Takeyoshi Masuda
发明人： Takeyoshi Masuda
IPC分类号： H01L21/336 , H01L29/16 , H01L29/04 , H01L29/423 , H01L29/66 , H01L29/739 , H01L29/78 , H01L29/861 , H01L21/3065 , H01L21/04 , H01L29/06
CPC分类号： H01L29/1608 , H01L21/0445 , H01L21/3065 , H01L29/045 , H01L29/0623 , H01L29/4236 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/8613 , Y10S438/931
摘要： A method for manufacturing a high-quality semiconductor device having stable characteristics is provided. The method for manufacturing the semiconductor device includes the steps of: preparing a silicon carbide layer having a main surface; forming a trench in the main surface by removing a portion of the silicon carbide layer; and removing a portion of a side wall of the trench by thermal etching.
摘要翻译：提供了一种制造具有稳定特性的高质量半导体器件的方法。制造半导体器件的方法包括以下步骤：制备具有主表面的碳化硅层; 通过去除一部分碳化硅层在主表面上形成沟槽; 以及通过热蚀刻去除沟槽的侧壁的一部分。

3. 发明授权

US08999854B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08999854B2
公开(公告)日：2015-04-07
申请号：US13658583
申请日：2012-10-23
申请人： Sumitomo Electric Industries, Ltd. , National University Corporation Nara Institute of Science and Technology
发明人： Takeyoshi Masuda , Tomoaki Hatayama
IPC分类号： H01L21/302 , H01L29/861 , H01L29/78 , H01L29/06 , H01L29/868 , H01L29/739 , H01L21/308 , H01L21/3065 , H01L29/12 , H01L21/02 , H01L29/16
CPC分类号： H01L29/8613 , H01L21/02529 , H01L21/02576 , H01L21/0262 , H01L21/0475 , H01L21/3065 , H01L21/3083 , H01L29/045 , H01L29/06 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0661 , H01L29/12 , H01L29/1608 , H01L29/4236 , H01L29/4238 , H01L29/66068 , H01L29/739 , H01L29/78 , H01L29/7813 , H01L29/861 , H01L29/868 , Y10S438/931
摘要： On a substrate, a silicon carbide layer provided with a main surface is formed. A mask is formed to cover a portion of the main surface of the silicon carbide layer. The main surface of the silicon carbide layer on which the mask is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer with a side surface inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.
摘要翻译：在基板上形成具有主表面的碳化硅层。形成掩模以覆盖碳化硅层的主表面的一部分。利用氯系气体对其上形成有掩模的碳化硅层的主表面进行热蚀刻，从而为碳化硅层提供相对于主表面倾斜的侧表面。热蚀刻步骤在氯系气体的分压为50％以下的气氛中进行。

4. 发明授权

US08703566B2 Transistors comprising a SiC-containing channel 有权
标题翻译：晶体管包括含SiC通道
公开(公告)号：US08703566B2
公开(公告)日：2014-04-22
申请号：US13901719
申请日：2013-05-24
申请人： Micron Technology, Inc.
发明人： Chandra Mouli
IPC分类号： H01L21/336
CPC分类号： H01L29/66666 , H01L21/8213 , H01L27/105 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/1054 , H01L29/1608 , H01L29/165 , H01L29/41783 , H01L29/4236 , H01L29/7827 , H01L29/785 , Y10S438/931
摘要： A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
摘要翻译：存储器件包括存储器单元阵列和外围设备。至少一些单独的记忆单元包括含有SiC的碳酸化部分。至少一些外围设备不包括任何碳酸化部分。晶体管包括第一源极/漏极，第二源极/漏极，包括在第一和第二源极/漏极之间包含SiC的半导体衬底的碳酸化部分的沟道以及与沟道的相对侧可操作地相关联的栅极。

5. 发明申请

US20130341646A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20130341646A1
公开(公告)日：2013-12-26
申请号：US13895848
申请日：2013-05-16
申请人： Sumitomo Electric Industries, Ltd.
发明人： Shunsuke Yamada , Hideto Tamaso
IPC分类号： H01L29/16 , H01L21/3205
CPC分类号： H01L29/1608 , H01L21/0485 , H01L21/32053 , H01L29/45 , H01L29/66068 , H01L29/7802 , Y10S438/931
摘要： A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device.
摘要翻译：碳化硅半导体器件包括碳化硅衬底和接触电极。碳化硅衬底包括与n型区域接触的n型区域和p型区域。接触电极与n型区域和p型区域接触。接触电极含有Ni原子和Si原子。 Ni原子数不小于Ni原子和Si原子总数的87％且不超过92％。因此，可以提供能够实现与n型杂质区域的欧姆接触并且可以实现p型杂质区域的低接触电阻的碳化硅半导体器件，以及制造这种碳化硅半导体器件的方法。

6. 发明申请

US20130248225A1 Laser Ablation Technique for Electrical Contact to Buried Electrically Conducting Layers in Diamond 有权
标题翻译：激光烧蚀技术在金刚石埋地导电层电接触
公开(公告)号：US20130248225A1
公开(公告)日：2013-09-26
申请号：US13801495
申请日：2013-03-13
申请人： Bradford B. Pate , Matthew P. Ray , Jeffrey W. Baldwin
发明人： Bradford B. Pate , Matthew P. Ray , Jeffrey W. Baldwin
IPC分类号： H05K3/46
CPC分类号： H05K1/09 , B23K26/06 , B23K26/0622 , B23K26/361 , B23K26/362 , B23K26/40 , B23K26/402 , B23K26/53 , B23K2101/38 , B23K2101/40 , B23K2103/50 , C30B29/04 , C30B33/02 , H01L23/3732 , H01L29/1602 , H01L29/1608 , H01L2924/00 , H01L2924/0002 , H05K3/0029 , H05K3/4602 , H05K2201/0323 , Y10S438/931 , Y10T428/265 , Y10T428/30
摘要： A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.
摘要翻译：一种用于与金刚石中的掩埋导电层进行电接触的激光烧蚀的方法，包括抛光具有第一碳表面的单晶金刚石衬底，用180KeV的光束注入金刚石，然后以4×1015的流通度注入150KeV C +离子离子/ cm 2和5×10 15离子/ cm 2，在第一碳表面下形成导电碳层，并且消除位于导电层和第一碳表面之间的单晶金刚石。

7. 发明授权

US08476697B1 Short-channel silicon carbide power MOSFET 有权
标题翻译：短沟碳化硅功率MOSFET
公开(公告)号：US08476697B1
公开(公告)日：2013-07-02
申请号：US13418028
申请日：2012-03-12
申请人： James A. Cooper , Maherin Matin
发明人： James A. Cooper , Maherin Matin
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L29/66068 , H01L29/7802 , Y10S438/931
摘要： A silicon carbide power MOSFET having a drain region of a first conductivity type, a base region of a second conductivity type above the drain region, and a source region of the first conductivity type adjacent an upper surface of the base region, the base region including a channel extending from the source region through the base region adjacent a gate interface surface thereof, the channel having a length less than approximately 0.6 μm, and the base region having a doping concentration of the second conductivity type sufficiently high that the potential barrier at the source end of the channel is not lowered by the voltage applied to the drain. The MOSFET includes self-aligned base and source regions as well as self-aligned ohmic contacts to the base and source regions.
摘要翻译：具有第一导电类型的漏极区域，位于漏极区域之上的第二导电类型的基极区域和与该基极区域的上表面相邻的第一导电类型的源极区域的碳化硅功率MOSFET，所述基极区域包括从源极区域延伸通过与其栅极界面表面相邻的基极区域的沟道，沟道具有小于约0.6μm的长度，并且具有足够高的第二导电类型的掺杂浓度的基极区域使得在通道的源极端不被施加到漏极的电压降低。 MOSFET包括自对准的基极和源极区域以及到基极和源极区域的自对准欧姆接触。

8. 发明申请

US20130130482A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20130130482A1
公开(公告)日：2013-05-23
申请号：US13658583
申请日：2012-10-23
申请人： Sumitomo Electric Industries, Ltd. , National University Corporation Nara Institute of
发明人： Takeyoshi Masuda , Tomoaki Hatayama
IPC分类号： H01L21/3065
CPC分类号： H01L29/8613 , H01L21/02529 , H01L21/02576 , H01L21/0262 , H01L21/0475 , H01L21/3065 , H01L21/3083 , H01L29/045 , H01L29/06 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0661 , H01L29/12 , H01L29/1608 , H01L29/4236 , H01L29/4238 , H01L29/66068 , H01L29/739 , H01L29/78 , H01L29/7813 , H01L29/861 , H01L29/868 , Y10S438/931
摘要： On a substrate, a silicon carbide layer provided with a main surface is formed. A mask is formed to cover a portion of the main surface of the silicon carbide layer. The main surface of the silicon carbide layer on which the mask is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer with a side surface inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.
摘要翻译：在基板上形成具有主表面的碳化硅层。形成掩模以覆盖碳化硅层的主表面的一部分。利用氯系气体对其上形成有掩模的碳化硅层的主表面进行热蚀刻，从而为碳化硅层提供相对于主表面倾斜的侧表面。热蚀刻步骤在氯系气体的分压为50％以下的气氛中进行。

9. 发明授权

US08415722B2 Memory devices and memory cells 有权
标题翻译：内存设备和内存单元
公开(公告)号：US08415722B2
公开(公告)日：2013-04-09
申请号：US13301921
申请日：2011-11-22
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L21/8213 , H01L27/105 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/1054 , H01L29/1608 , H01L29/165 , H01L29/41783 , H01L29/4236 , H01L29/7827 , H01L29/785 , Y10S438/931
摘要： A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
摘要翻译：存储器件包括存储器单元阵列和外围设备。至少一些单独的记忆单元包括含有SiC的碳酸化部分。至少一些外围设备不包括任何碳酸化部分。晶体管包括第一源极/漏极，第二源极/漏极，包括在第一和第二源极/漏极之间包含SiC的半导体衬底的碳酸化部分的沟道以及与沟道的相对侧可操作地相关联的栅极。

10. 发明授权

US08389376B2 Air gap integration scheme 有权
标题翻译：气隙整合方案
公开(公告)号：US08389376B2
公开(公告)日：2013-03-05
申请号：US12714865
申请日：2010-03-01
申请人： Alexandros T. Demos , Li-Qun Xia , Bok Hoen Kim , Derek R. Witty , Hichem M'Saad
发明人： Alexandros T. Demos , Li-Qun Xia , Bok Hoen Kim , Derek R. Witty , Hichem M'Saad
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , C23C16/401 , C23C16/56 , H01L21/02115 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02351 , H01L21/02362 , H01L21/3146 , H01L21/31633 , H01L21/31695 , H01L21/76811 , H01L21/76835 , H01L2221/1047 , Y10S438/931
摘要： Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure including depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.
摘要翻译：提供了用于形成包括气隙的结构的方法。在一个实施方案中，提供了一种用于形成镶嵌结构的方法，包括通过包括使有机硅化合物和致孔剂提供前体反应的方法沉积多孔低介电常数层，沉积含致孔剂的材料，以及除去至少一部分含致孔剂的材料，通过使造孔剂提供前体反应，在有机层中形成特征定义和多孔低介电常数层，在多孔低介电常数层上沉积有机层，用导电材料填充特征定义在有机层上沉积掩模层和设置在特征定义中的导电材料，在掩模层中形成孔以暴露有机层，通过孔去除部分或全部有机层，并形成相邻的气隙导电材料。

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