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1. 发明授权

US06228725B1 Semiconductor devices with pocket implant and counter doping 有权
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US06228725B1
公开(公告)日：2001-05-08
申请号：US09281543
申请日：1999-03-30
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

2. 发明授权

US5917219A Semiconductor devices with pocket implant and counter doping 失效
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US5917219A
公开(公告)日：1999-06-29
申请号：US725599
申请日：1996-10-03
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L27/01 , H01L27/12 , H01L31/0397
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

3. 发明授权

US06960499B2 Dual-counterdoped channel field effect transistor and method 有权
标题翻译：双对流通道场效应晶体管及方法
公开(公告)号：US06960499B2
公开(公告)日：2005-11-01
申请号：US10866469
申请日：2004-06-14
申请人： Mahalingam Nandakumar , Karthik Vasanth , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Karthik Vasanth , Ih-Chin Chen
IPC分类号： H01L21/265 , H01L29/10 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/1033
摘要： A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.
摘要翻译：公开了一种具有双重反向通道的场效应晶体管。晶体管具有包括第一掺杂区域（28）和位于第一掺杂区域下方的第二掺杂区域（26）的沟道。源极和漏极（32）形成在与沟道相邻的位置。在本发明的一个实施例中，第一掺杂区域（28）掺杂有砷，而第二掺杂区域（26）掺杂有磷。地下通道层（28）的高电荷载流子迁移率允许使用较低的沟道掺杂剂浓度，这又允许较低的源极/漏极口袋掺杂。这降低了晶体管的电容和响应时间。

4. 发明授权

US06258644B1 Mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps 有权
标题翻译：混合电压CMOS工艺，用于高可靠性和高性能的核心和I / O晶体管，减少了掩模步骤
公开(公告)号：US06258644B1
公开(公告)日：2001-07-10
申请号：US09499719
申请日：2000-02-08
申请人： Mark S. Rodder , Manoj Mehrotra , Mahalingam Nandakumar
发明人： Mark S. Rodder , Manoj Mehrotra , Mahalingam Nandakumar
IPC分类号： H01L218238
CPC分类号： H01L21/823814
摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.
摘要翻译：用于高可靠性和高性能核心晶体管和输入输出晶体管的混合电压CMOS工艺，减少了掩模步骤。在硅衬底（10）上形成栅叠层（30）。对第一种和第二种进行离子注入，以在输入输出晶体管中产生掺杂分布（70,80,90,100）。

5. 发明授权

US06306712B1 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing 有权
标题翻译：改善CMOS的侧壁工艺和植入方法，有利于低CGD，改善掺杂特性和对化学处理的不敏感性
公开(公告)号：US06306712B1
公开(公告)日：2001-10-23
申请号：US09205637
申请日：1998-12-03
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/26586 , H01L29/0847 , H01L29/1083 , H01L29/4983 , H01L29/66545 , H01L29/6656 , H01L29/66628 , Y10S438/926 , Y10S438/931
摘要： A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).
摘要翻译：本文公开了一种用于使用边缘阻挡材料（24）形成晶体管的晶体管（30）和方法。边缘阻挡材料（24）可以位于邻近门（22）或一次性门，或者可以是一次性门的一部分。在成角度的袋式注入期间，边缘阻挡材料（24）阻挡一些掺杂剂进入半导体本体（10），并且位于边缘阻挡材料下面的掺杂剂（18）位于半导体本体表面下方给定的距离处 10）。

6. 发明授权

US5976937A Transistor having ultrashallow source and drain junctions with reduced gate overlap and method 有权
标题翻译：具有超低源极和漏极结的晶体管具有减少的栅极重叠和方法
公开(公告)号：US5976937A
公开(公告)日：1999-11-02
申请号：US136750
申请日：1998-08-19
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/1083 , H01L21/26586 , H01L21/823418 , H01L29/66492 , H01L29/6659
摘要： Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126). The dopants are implanted in the first direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (166 and 168) of the second active area (142). Dopants may be implanted from a second direction substantially parallel to the second gate electrode (140) and perpendicular to the first direction into the source and drain sections (166 and 168) of the second active area (142). The dopants are implanted in the second direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (162 and 164) of the first active area (126).
摘要翻译：制造具有减少的栅极重叠的超短源极和漏极结的晶体管的方法可以包括通过第一栅极绝缘体（130）形成与半导体层（112）的第一有源区（126）分离的第一栅电极（124）。第二栅极电极（140）可以形成为基本上垂直于第一栅电极（124）并且通过第二栅极绝缘体（146）与半导体层的第二有源区域（142）分离。可以在半导体层（112）之上形成掩模层（160）并且暴露第一有源区域（126）的源极和漏极部分（162和164）以及源极和漏极部分（166和168）第二活动区域（142）。掺杂剂可以从基本上平行于第一栅电极（124）的第一方向注入到第一有源区（126）的源区和漏区（166和168）中。所述掺杂剂以所述掩蔽层（160）阻止所述掺杂剂进入所述第二有源区域（142）的源极和漏极部分（166和168）的角度沿所述第一方向植入。掺杂剂可以从基本上平行于第二栅电极（140）并垂直于第一方向的第二方向注入第二有源区（142）的源区和漏区（166和168）中。所述掺杂剂以所述掩蔽层（160）阻挡所述掺杂剂进入所述第一有源区（126）的源区和漏区（162和164）的角度在第二方向上注入。

7. 发明授权

US06579770B2 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing 有权
标题翻译：改善CMOS的侧壁工艺和植入方法，有利于低CGD，改善掺杂特性和对化学处理的不敏感性
公开(公告)号：US06579770B2
公开(公告)日：2003-06-17
申请号：US09899783
申请日：2001-07-05
申请人： Mark S. Rodder , Mahalingam Nandakumar
发明人： Mark S. Rodder , Mahalingam Nandakumar
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/26586 , H01L29/0847 , H01L29/1083 , H01L29/4983 , H01L29/66545 , H01L29/6656 , H01L29/66628 , Y10S438/926 , Y10S438/931
摘要： A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).
摘要翻译：本文公开了一种用于使用边缘阻挡材料（24）形成晶体管的晶体管（30）和方法。边缘阻挡材料（24）可以位于邻近门（22）或一次性门，或者可以是一次性门的一部分。在成角度的袋式注入期间，边缘阻挡材料（24）阻挡一些掺杂剂进入半导体本体（10），并且位于边缘阻挡材料下面的掺杂剂（18）位于半导体本体表面下方给定的距离处 10）。

8. 发明授权

US07638402B2 Sidewall spacer pullback scheme 有权
标题翻译：侧壁间隔回拉方案
公开(公告)号：US07638402B2
公开(公告)日：2009-12-29
申请号：US11728928
申请日：2007-03-27
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
IPC分类号： H01L21/336
CPC分类号： H01L21/823468 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.
摘要翻译：在形成晶体管时实现侧壁间隔器回拉方案。除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。

9. 发明申请

US20080160708A1 Sidewall spacer pullback scheme 有权
标题翻译：侧壁间隔回拉方案
公开(公告)号：US20080160708A1
公开(公告)日：2008-07-03
申请号：US11728928
申请日：2007-03-27
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
IPC分类号： H01L21/336
CPC分类号： H01L21/823468 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.
摘要翻译：在形成晶体管时实现侧壁间隔器回拉方案。除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。

10. 发明授权

US06713334B2 Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask 有权
标题翻译：在高电压屏蔽下，使用额外的注入芯片制造双电压CMOSFET
公开(公告)号：US06713334B2
公开(公告)日：2004-03-30
申请号：US10215925
申请日：2002-08-09
申请人： Mahalingam Nandakumar , Youngmin Kim , Amitava Chatterjee
发明人： Mahalingam Nandakumar , Youngmin Kim , Amitava Chatterjee
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/823857
摘要： An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.
摘要翻译：提供HVGX模式的植入（步骤102c）以允许在核心晶体管上选择性晶体管阈值电压Vth调节，而不影响I / O晶体管阈值电压Vt。注入提供独立调谐的NMOS核心晶体管和I / O晶体管Vth或 PMOS晶体管和I / O晶体管Vth。

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