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1. 发明申请

US20220211179A1 Active Posture Management 有权
公开(公告)号：US20220211179A1
公开(公告)日：2022-07-07
申请号：US17249689
申请日：2021-03-10
申请人： Karthik Vasanth
发明人： Keshav Vasanth
IPC分类号： A47C7/46 , G05B6/02 , G01V8/10 , G01S15/04
摘要： An apparatus for managing posture may comprise a back support, a sensor unit coupled to the back support, a posture manipulator coupled to the back support, and a controller coupled to the sensor unit and to the posture manipulator. The controller may be configured to receive a feedback signal from the sensor unit indicative of posture, and to operate the posture manipulator based on the feedback signal. Some embodiments of the apparatus may be configured to compare the feedback signal to a posture model and operate the posture model based on a difference between the feedback signal and the posture model. The sensor unit may comprise one or more sensors for determining various biometric and biomechanical parameters.

2. 发明授权

US06960499B2 Dual-counterdoped channel field effect transistor and method 有权
标题翻译：双对流通道场效应晶体管及方法
公开(公告)号：US06960499B2
公开(公告)日：2005-11-01
申请号：US10866469
申请日：2004-06-14
申请人： Mahalingam Nandakumar , Karthik Vasanth , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Karthik Vasanth , Ih-Chin Chen
IPC分类号： H01L21/265 , H01L29/10 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/1033
摘要： A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.
摘要翻译：公开了一种具有双重反向通道的场效应晶体管。晶体管具有包括第一掺杂区域（28）和位于第一掺杂区域下方的第二掺杂区域（26）的沟道。源极和漏极（32）形成在与沟道相邻的位置。在本发明的一个实施例中，第一掺杂区域（28）掺杂有砷，而第二掺杂区域（26）掺杂有磷。地下通道层（28）的高电荷载流子迁移率允许使用较低的沟道掺杂剂浓度，这又允许较低的源极/漏极口袋掺杂。这降低了晶体管的电容和响应时间。

3. 发明授权

US06530064B1 Method and apparatus for predicting an operational lifetime of a transistor 失效
标题翻译：用于预测晶体管的工作寿命的方法和装置
公开(公告)号：US06530064B1
公开(公告)日：2003-03-04
申请号：US09692692
申请日：2000-10-19
申请人： Karthik Vasanth , Shian-Wei Aur , E. Ajith Amerasekera , Sharad Saxena , Joseph C. Davis , Richard G. Burch
发明人： Karthik Vasanth , Shian-Wei Aur , E. Ajith Amerasekera , Sharad Saxena , Joseph C. Davis , Richard G. Burch
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/18
摘要： An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design (10) and a specified set of fabrication process conditions (117), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap (12) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.
摘要翻译：无需实际制造和测试根据特定设计数据和过程制造的物理晶体管，可以准确预测实验晶体管设计（10）和指定的制造工艺条件（117）集合的运行寿命和性能特性条件。关于工作寿命的预测，可以将工作寿命表示为晶体管的栅极重叠（12）的大小的函数，并且该关系在设计晶体管的所选择的半导体技术中是有效的。通过选择两个处理条件的值的组合来确定栅极重叠的大小。

4. 发明授权

US09157897B2 High voltage ultrasound transmitter with gate protection diodes and intrinsic output zeroing 有权
标题翻译：具有栅极保护二极管和内部输出调零的高压超声波发射器
公开(公告)号：US09157897B2
公开(公告)日：2015-10-13
申请号：US12582752
申请日：2009-10-21
申请人： Ismail H. Oguzman , Arash Loloee , Suribhotla Rajasekhar , Karthik Vasanth
发明人： Ismail H. Oguzman , Arash Loloee , Suribhotla Rajasekhar , Karthik Vasanth
IPC分类号： A61B8/00 , G01N29/32 , B06B1/02 , G01N29/06 , G01N29/34
CPC分类号： G01N29/32 , A61B8/4483 , B06B1/023 , G01N29/06 , G01N29/34
摘要： An ultrasound transmitter including intrinsic output zeroing is disclosed herein. A transmitter for generating ultrasound signals includes a first transmitter output driver and a first transmitter input driver. The first transmitter output driver includes an N-type device serially coupled to a P-type device. The first transmitter input driver includes an N-type device serially coupled to a P-type device. An output of the first transmitter input driver is coupled to an input of the first transmitter output driver. The first transmitter output driver drives an output of the transmitter to a first voltage and the first transmitter input driver drives the output of the transmitter to a second voltage while the first transmitter output driver is disabled.
摘要翻译：本文公开了包括固有输出调零的超声波发射器。用于产生超声信号的发射器包括第一发射器输出驱动器和第一发射器输入驱动器。第一发射机输出驱动器包括串联耦合到P型装置的N型装置。第一发射机输入驱动器包括串联耦合到P型装置的N型装置。第一发射机输入驱动器的输出耦合到第一发射机输出驱动器的输入端。第一发射机输出驱动器将发射机的输出驱动到第一电压，而第一发射机输入驱动器被禁用时，第一发射机输入驱动器将发射机的输出驱动到第二电压。

5. 发明授权

US06311096B1 Design of microelectronic process flows for manufacturability and performance 有权
标题翻译：微电子工艺流程的可制造性和性能设计
公开(公告)号：US06311096B1
公开(公告)日：2001-10-30
申请号：US09283479
申请日：1999-04-01
申请人： Sharad Saxena , Karthik Vasanth , Richard G. Burch , Purnendu K. Mozumder , Suraj Rao , Joseph C. Davis
发明人： Sharad Saxena , Karthik Vasanth , Richard G. Burch , Purnendu K. Mozumder , Suraj Rao , Joseph C. Davis
IPC分类号： G06F1900
CPC分类号： G06Q10/06
摘要： A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.
摘要翻译：提供统计设计方法，用于通过统计设计来最小化制造差异对半导体制造的影响，其旨在减少变异性对器件行为的影响。该方法基于处理流程的马尔科夫表示，其捕获半导体制造的顺序和随机性质，并且能够分离设备和过程模型，将过程模块从可观察的晶片状态进行统计建模以及用于大型设计空间的统计优化的近似。该方法的统计估计分量导致了对所有制造流量的晶体管性能的可变性的非常准确的预测。统计优化可以实现所有晶体管性能和可靠性目标的器件，并减少关键晶体管性能的变化。

6. 发明授权

US6157062A Integrating dual supply voltage by removing the drain extender implant from the high voltage device 有权
标题翻译：通过从高压设备中移除漏极延长器植入物来整合双电源电压
公开(公告)号：US6157062A
公开(公告)日：2000-12-05
申请号：US287227
申请日：1999-04-06
申请人： Karthik Vasanth , Richard G. Burch , Sharad Saxena , Purnendu K. Mozumder , Chenjing L. Fernando , Joseph C. Davis , Suraj Rao
发明人： Karthik Vasanth , Richard G. Burch , Sharad Saxena , Purnendu K. Mozumder , Chenjing L. Fernando , Joseph C. Davis , Suraj Rao
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L29/76
CPC分类号： H01L21/823418 , H01L21/8238
摘要： A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.
摘要翻译：通过调整栅极侧壁间隔物厚度和源极/漏极注入，在高电压晶体管中制造双电压芯片，其中没有中间掺杂（LDD或MDD）区域。

7. 发明授权

US06388288B1 Integrating dual supply voltages using a single extra mask level 有权
标题翻译：使用单个额外的掩模级别集成双电源电压
公开(公告)号：US06388288B1
公开(公告)日：2002-05-14
申请号：US09276783
申请日：1999-03-25
申请人： Karthik Vasanth , Sharad Saxena , Richard G. Burch , Purnendu K. Mozumder , Joseph C. Davis , Chenjing L. Fernando , Suraj Rao
发明人： Karthik Vasanth , Sharad Saxena , Richard G. Burch , Purnendu K. Mozumder , Joseph C. Davis , Chenjing L. Fernando , Suraj Rao
IPC分类号： H01L2976
CPC分类号： H01L21/823418
摘要： Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.
摘要翻译：通过仅对周围晶体管的MDD注入进行优化，可以通过最小额外的掩模来实现双电压集成在一起，而对于两种晶体管类型，其他植入物保持相同。这符合生命周期规格，无需费用。

8. 发明申请

US20110088475A1 TRANSMITTER WITH INTRINSIC OUTPUT ZEROING 有权
标题翻译：具有内部输出零点的变送器
公开(公告)号：US20110088475A1
公开(公告)日：2011-04-21
申请号：US12582752
申请日：2009-10-21
申请人： Ismail H. OGUZMAN , Arash LOLOEE , Suribhotla RAJASEKHAR , Karthik VASANTH
发明人： Ismail H. OGUZMAN , Arash LOLOEE , Suribhotla RAJASEKHAR , Karthik VASANTH
IPC分类号： G01N29/00 , G06K9/00
CPC分类号： G01N29/32 , A61B8/4483 , B06B1/023 , G01N29/06 , G01N29/34
摘要： An ultrasound transmitter including intrinsic output zeroing is disclosed herein. A transmitter for generating ultrasound signals includes a first transmitter output driver and a first transmitter input driver. The first transmitter output driver includes an N-type device serially coupled to a P-type device. The first transmitter input driver includes an N-type device serially coupled to a P-type device. An output of the first transmitter input driver is coupled to an input of the first transmitter output driver. The first transmitter output driver drives an output of the transmitter to a first voltage and the first transmitter input driver drives the output of the transmitter to a second voltage while the first transmitter output driver is disabled.
摘要翻译：本文公开了包括固有输出调零的超声波发射器。用于产生超声信号的发射器包括第一发射器输出驱动器和第一发射器输入驱动器。第一发射机输出驱动器包括串联耦合到P型装置的N型装置。第一发射机输入驱动器包括串联耦合到P型装置的N型装置。第一发射机输入驱动器的输出耦合到第一发射机输出驱动器的输入端。第一发射机输出驱动器将发射机的输出驱动到第一电压，而第一发射机输入驱动器被禁用时，第一发射机输入驱动器将发射机的输出驱动到第二电压。

9. 发明授权

US06381564B1 Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators 有权
标题翻译：使用响应面方法确定复杂模拟器的最佳调谐参数的方法和系统
公开(公告)号：US06381564B1
公开(公告)日：2002-04-30
申请号：US09304189
申请日：1999-05-03
申请人： Joseph C. Davis , Karthik Vasanth , Sharad Saxena , Purnendu K. Mozumder , Suraj Rao , Chenjing L. Fernando , Richard G. Burch
发明人： Joseph C. Davis , Karthik Vasanth , Sharad Saxena , Purnendu K. Mozumder , Suraj Rao , Chenjing L. Fernando , Richard G. Burch
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation. The objective function is, for example, the square root of the sum of the squares at all of the differences between the target values and the observed values at all points being investigated. The optimizing in the optimizer is preferably a gain function which adjusts the parameters to the input based upon the error signal to minimize the error signal.
摘要翻译：一种用于为复杂模拟器提供最佳调谐的方法和系统。该方法和系统包括最初构建至少一个具有输入和输出端的RSM模型。然后，通过从至少一个RSM模型的输出端子和实验数据的输出构造目标函数来提供无模拟优化功能。目标函数在优化器中进行优化，优化的目标函数馈送到RSM的输入端。建立至少一个RSM模型，包括建立模拟范围，运行设计实验的仿真实验，从所提取的实验中提取相关数据，并从提取的相关数据构建RSM模型。运行模拟实验的步骤包括运行DOE / Opt操作的步骤。目标函数例如是目标值与被调查的所有点的观测值之间的所有差异的平方和的平方根。优化器中的优化优选地是基于误差信号调整输入参数的增益函数，以最小化误差信号。

10. 发明授权

US06317640B1 System and method for non-parametric modeling of processed induced variability 有权
标题翻译：加工诱导变异性非参数建模的系统和方法
公开(公告)号：US06317640B1
公开(公告)日：2001-11-13
申请号：US09225877
申请日：1999-01-05
申请人： Suraj Rao , Sharad Saxena , Pushkar P. Apte , Purnendu K. Mozumder , Richard Gene Burch , Karthik Vasanth , Joseph Carl Davis , Chenjing L. Fernando
发明人： Suraj Rao , Sharad Saxena , Pushkar P. Apte , Purnendu K. Mozumder , Richard Gene Burch , Karthik Vasanth , Joseph Carl Davis , Chenjing L. Fernando
IPC分类号： G06F1900
CPC分类号： G06F17/5009 , G06F2217/10
摘要： Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.
摘要翻译：公开了用于充分建模过程诱导变异性的方法，其包括获取实验数据和定义特定设计空间的步骤。计算定义设计空间的每个点的实验数据的平均值和标准偏差的值。将每个设计点的输出参数的实验值归一化以提取每个设计点的分布形状。然后将归一化值合并以形成与数据相关联的累积分布函数。通过从实验数据的平均值和标准偏差值内插，首先计算新点的平均值和标准偏差值，累积分布函数以预测方式应用于新设计点。然后使用插值的平均值和标准偏差值对累积分布函数进行缩放和居中，以提供新设计点的预测数据分布。

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