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21. 发明授权

US5834350A Elevated transistor fabrication technique 失效
公开(公告)号：US5834350A
公开(公告)日：1998-11-10
申请号：US873116
申请日：1997-06-11
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/822 , H01L27/06 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

22. 发明授权

US5677224A Method of making asymmetrical N-channel and P-channel devices 失效
标题翻译：制造不对称N沟道和P沟道器件的方法
公开(公告)号：US5677224A
公开(公告)日：1997-10-14
申请号：US711381
申请日：1996-09-03
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/70
CPC分类号： H01L21/823814 , H01L27/0922
摘要： An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped source region and lightly doped drain region provide channel junctions. Forming a first asymmetrical IGFET includes forming a gate with first and second opposing sidewalls over a first active region, applying a first ion implantation to implant lightly doped source and drain regions into the first active region, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. A second asymmetrical IGFET is formed in a related manner. Advantageously, one or both IGFETs have low source-drain series resistance and reduce hot carrier effects.
摘要翻译：公开了非对称N沟道IGFET和非对称P沟道IGFET。一个或两个IGFET包括轻掺杂漏极区，重掺杂源极和漏极区以及超重掺杂源极区。优选地，重掺杂源极区域和轻掺杂漏极区域提供沟道结。形成第一不对称IGFET包括在第一有源区上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂源极和漏极区域注入到第一有源区中，施加第二离子注入以将所述轻掺杂源区分别成为重掺杂源区，而不掺杂所述轻掺杂漏区，分别与所述第一和第二侧壁相邻形成第一和第二间隔区，并施加第三离子注入以转换所述重掺杂源区的一部分在第一间隔物之外的第一间隔物外部，而不掺杂第一间隔物下面的重掺杂源区的一部分，并将第二间隔区外部的轻掺杂漏极区的一部分转换成重掺杂漏极区，而不掺杂第二间隔物下面的轻掺杂漏极区的一部分。以相关的方式形成第二不对称IGFET。有利地，一个或两个IGFET具有低的源 - 漏串联电阻并且减少热载流子效应。

23. 发明授权

US5654215A Method for fabrication of a non-symmetrical transistor 失效
标题翻译：制造非对称晶体管的方法
公开(公告)号：US5654215A
公开(公告)日：1997-08-05
申请号：US713388
申请日：1996-09-13
申请人： Mark I. Gardner , Daniel Kadosh , Robert Dawson
发明人： Mark I. Gardner , Daniel Kadosh , Robert Dawson
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823468 , H01L29/7835 , Y10S438/911
摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, a gate insulator and a gate electrode, such as a polysilicon, are formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall. First and second symmetrical spacers are then formed adjacent the first and second sidewalls, respectively. A second dopant is implanted into the semiconductor substrate after forming the symmetrical spacers to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer. After implanting the second dopant, first and second non-symmetrical spacers are formed adjacent the first and second sidewalls, respectively. A heavy dose of a third dopant is then implanted into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region. In another embodiment, a fourth dopant is implanted into the semiconductor substrate before forming the first and second symmetrical spacers further doping the lightly doped drain region.
摘要翻译：在本发明中，描述了用于制造非对称LDD-IGFET的方法。在一个实施例中，栅极绝缘体和诸如多晶硅的栅电极形成在半导体衬底之上，栅电极具有顶表面和相对的第一和第二侧壁。将第一掺杂剂注入到半导体衬底中以提供基本上与第二侧壁对齐的轻掺杂漏极区。然后分别在第一和第二侧壁附近形成第一和第二对称间隔物。在形成对称间隔物之后，将第二掺杂剂注入到半导体衬底中，以提供基本上与第二对称间隔物的外部区域对准的适度轻掺杂的漏区。在注入第二掺杂剂之后，分别在第一和第二侧壁附近形成第一和第二非对称间隔物。然后将大量的第三掺杂剂注入到半导体衬底中以提供重掺杂的源极区域和重掺杂的漏极区域。在另一个实施例中，在形成第一和第二对称间隔物之前将第四掺杂剂注入到半导体衬底中，进一步掺杂轻掺杂漏极区。

24. 发明授权

US06261885B1 Method for forming integrated circuit gate conductors from dual layers of polysilicon 有权
标题翻译：从双层多晶硅形成集成电路栅极导体的方法
公开(公告)号：US06261885B1
公开(公告)日：2001-07-17
申请号：US09497789
申请日：2000-02-03
申请人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
发明人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
IPC分类号： H01L218238
CPC分类号： H01L21/82345
摘要： A method for fabricating an integrated circuit is presented wherein a first polysilicon layer dielectrically spaced above a semiconductor substrate is provided. The semiconductor substrate contains a first active region and a second active region. A first dopant is selectively introduced into the portion of the first polysilicon layer above the second active region. A second polysilicon layer may then be formed upon the first polysilicon layer and above the first active region and the second active region. A second dopant may be selectively introduced into a portion of the second polysilicon layer above the first active region. The portion of the second polysilicon layer above the first active region and the portion of the first polysilicon layer above the first active region may be patterned to form a first gate structure within the first active region. The portion of the second polysilicon layer above the second active region and the portion of the first polysilicon layer above the second active region may be patterned to form a second gate structure within the second active region.
摘要翻译：提出了一种用于制造集成电路的方法，其中提供介于半导体衬底之上的第一多晶硅层。半导体衬底包含第一有源区和第二有源区。第一掺杂剂被选择性地引入第二有源区上方的第一多晶硅层的部分。然后可以在第一多晶硅层上并且在第一有源区和第二有源区上方形成第二多晶硅层。可以将第二掺杂剂选择性地引入第一有源区上方的第二多晶硅层的一部分。在第一有源区上方的第二多晶硅层的部分和第一有源区上方的第一多晶硅层的部分可以被图案化以在第一有源区内形成第一栅极结构。在第二有源区上方的第二多晶硅层的部分和第二有源区上方的第一多晶硅层的部分可以被图案化以在第二有源区内形成第二栅极结构。

25. 发明授权

US06172402B2 Integrated circuit having transistors that include insulative punchthrough regions and method of formation 失效
标题翻译：具有包括绝缘穿透区域和形成方法的晶体管的集成电路
公开(公告)号：US06172402B2
公开(公告)日：2001-01-09
申请号：US09090466
申请日：1998-06-04
申请人： Mark I. Gardner , Mark C. Gilmer , Daniel Kadosh
发明人： Mark I. Gardner , Mark C. Gilmer , Daniel Kadosh
IPC分类号： H01L2701
CPC分类号： H01L21/76237 , H01L21/823807 , H01L21/823878 , H01L27/0921
摘要： An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination. The transistors and other circuit elements formed in the substrate may be interconnected to form an integrated circuit.
摘要翻译：集成电路包括形成为包括绝缘穿透区域的多个晶体管。多个晶体管中的每一个包括形成在基板上的沟道，形成在沟道下方的绝缘穿透区域，形成在与沟道的第一端相邻的绝缘穿透区域上的源极，形成在绝缘穿透区域上的漏极，沟道的第二端，形成在沟道上方的栅极氧化物和形成在栅极氧化物上方的栅极导体。绝缘区域也可以形成在衬底中，其具有在形成绝缘穿通区域时形成的蚀刻停止定义。可以在栅极氧化物和沟道之间形成电压阈值区域，并且可以在沟道附近形成轻掺杂区域。绝缘穿透区域可以是氧化层，也可以形成在氧化物注入步骤中的衬底内，并形成蚀刻停止。形成在衬底中的晶体管和其它电路元件可以互连以形成集成电路。

26. 发明授权

US6111298A Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length 有权
标题翻译：蚀刻停止层形成在多层栅极导体内以提供通道长度的减小
公开(公告)号：US6111298A
公开(公告)日：2000-08-29
申请号：US145010
申请日：1998-09-01
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/51 , H01L29/76
CPC分类号： H01L29/518 , H01L21/28052 , H01L21/28176 , H01L21/823456 , H01L21/823828 , H01L21/82385 , H01L29/665 , H01L29/6659 , H01L29/66598 , Y10S438/97
摘要： A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.
摘要翻译：提供了一种用于形成晶体管栅极导体的工艺，该晶体管栅极导体具有布置在其上表面下方的深度处的蚀刻停止，使得蚀刻停止点之上的栅极导体的横向宽度可以专门变窄以提供晶体管沟道长度的减小。在栅极导体上形成图案的掩模层，即光致抗蚀剂被各向同性蚀刻，以便在蚀刻栅极导体之前将其横向宽度最小化。未被光致抗蚀剂保护的栅极导体的部分可以从蚀刻停止点的上方蚀刻，以限定用于栅极导体的上部的新的一对相对的侧壁表面。因此，栅极导体的上部的横向宽度可以减小到比常规栅极导体更小的尺寸。对栅极导体进行各向异性蚀刻，其中不被变窄的光致抗蚀剂保护的栅极导体的部分被蚀刻到蚀刻停止点。蚀刻停止的存在确保蚀刻停止的大部分和栅极导体的下面的部分在蚀刻完全终止之前不被去除。结果，多层栅极导体的下部比栅极导体的上部宽。

27. 发明授权

US6077748A Advanced trench isolation fabrication scheme for precision polysilicon gate control 有权
标题翻译：高级沟槽隔离制造方案，用于精密多晶硅栅极控制
公开(公告)号：US6077748A
公开(公告)日：2000-06-20
申请号：US174898
申请日：1998-10-19
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/266 , H01L21/336 , H01L21/762 , H01L21/22
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/76237
摘要： An IGFET device isolation structure fabrication scheme includes the formation of electrically insulating isolation structures that extend into the substrate and extend above the surface of the substrate. The isolation structures are formed by providing a first mask to form trenches in the substrate. A layer of silicon dioxide is then deposited, filling the trenches and extending above the surface of the substrate. A second mask layer is formed. The second mask layer shadows the trench regions that were formed in the substrate. The silicon dioxide not shadowed by the second mask layer is removed, leaving isolation structures that extend both into the substrate and which rise above the substrate. A gate structure is formed in the region between two isolation structures, and, in the preferred embodiment, the gate structure extends above the substrate to the same height as the isolation structures. The isolation structures and the gate structure can be used to provide self-aligned doped source/drain regions. Spacers can be added to the isolation structure walls and the gate structure walls to provide heavily-doped self-aligned regions.
摘要翻译： IGFET器件隔离结构制造方案包括形成延伸到衬底中并延伸到衬底表面之上的电绝缘隔离结构。通过提供第一掩模以在衬底中形成沟槽来形成隔离结构。然后沉积一层二氧化硅，填充沟槽并在衬底的表面上方延伸。形成第二掩模层。第二掩模层阴影在衬底中形成的沟槽区域。除去未被第二掩模层遮蔽的二氧化硅，留下隔离结构，其延伸到衬底中并且在衬底上方上升。在两个隔离结构之间的区域中形成栅极结构，并且在优选实施例中，栅极结构在衬底上方延伸到与隔离结构相同的高度。隔离结构和栅极结构可用于提供自对准的掺杂源极/漏极区域。可以将间隔物添加到隔离结构壁和栅极结构壁以提供重掺杂的自对准区域。

28. 发明授权

US6008096A Ultra short transistor fabrication method 失效
标题翻译：超短晶体管制造方法
公开(公告)号：US6008096A
公开(公告)日：1999-12-28
申请号：US790516
申请日：1997-01-29
申请人： Mark I. Gardner , Michael Duane , Daniel Kadosh
发明人： Mark I. Gardner , Michael Duane , Daniel Kadosh
IPC分类号： H01L21/225 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/66477 , H01L21/2256 , H01L21/2652 , H01L21/28141 , H01L21/823437 , H01L29/66545
摘要： A semiconductor process in which the transistor channel is defined by opposing sidewalls of a pair of masking structures formed on an upper surface of a semiconductor substrate. The spacing between the opposed sidewalls is defined by the thickness of the spacer structure formed between the sidewalls. The thickness of the spacer structure is preferably in the range of approximately 0.04 microns. A masking layer is formed on an upper surface of a semiconductor substrate. The masking layer includes first and second masking structures and a channel trench material. Opposing sidewalls of the first and second masking structures are laterally displaced by a channel displacement. The opposing sidewalls together with an upper surface of the semiconductor substrate define a channel trench. The channel trench is displaced above and aligned with a channel region of the semiconductor substrate. The channel trench material fills the channel trench. A mean projected path characteristic of the channel trench material is less than a mean projected path characteristic of the first and second masking structures. A source/drain impurity distribution is implanted into and through the masking layer to selectively introduce a source/drain impurity distribution into a source/drain region of the semiconductor substrate. The source/drain regions of the semiconductor substrate are laterally displaced on either side of the channel region. The channel trench material is then removed and a gate dielectric layer is formed on the floor of the channel trench. Thereafter, the channel trench is filled with a conductive material to form a conductive gate on the gate dielectric.
摘要翻译：一种半导体工艺，其中晶体管沟道由形成在半导体衬底的上表面上的一对掩模结构的相对侧壁限定。相对侧壁之间的间隔由形成在侧壁之间的间隔结构的厚度限定。间隔物结构的厚度优选在约0.04微米的范围内。掩模层形成在半导体衬底的上表面上。掩模层包括第一和第二掩模结构和通道沟槽材料。第一和第二掩蔽结构的相对侧壁被通道位移横向移位。相对的侧壁与半导体衬底的上表面一起形成通道沟槽。沟道沟槽位于半导体衬底的沟道区上方并与之对齐。通道沟槽材料填充沟槽。通道沟槽材料的平均投影路径特性小于第一和第二掩模结构的平均投影路径特性。源极/漏极杂质分布被注入并穿过掩模层，以选择性地将源极/漏极杂质分布引入到半导体衬底的源极/漏极区域中。半导体衬底的源极/漏极区域在沟道区域的任一侧上被横向移位。然后去除沟道沟槽材料，并且在沟道沟槽的底板上形成栅极电介质层。此后，沟道沟槽填充有导电材料，以在栅极电介质上形成导电栅极。

29. 发明授权

US5969394A Method and structure for high aspect gate and short channel length insulated gate field effect transistors 失效
标题翻译：高截面栅极和短沟道长度绝缘栅场效应晶体管的方法和结构
公开(公告)号：US5969394A
公开(公告)日：1999-10-19
申请号：US993385
申请日：1997-12-18
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/223 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28194 , H01L21/223 , H01L29/42364 , H01L29/66659 , H01L29/7835 , H01L29/51 , H01L29/665
摘要： A method and structure are provided for an IGFET which has a short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Also the invention includes a dielectric layer with a high dielectric constant value (K) to prolong the longevity of the device. A lightly doped drain region similarly preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.
摘要翻译：为具有短导电沟道长度的IGFET提供了一种方法和结构。短通道IGFET的功能比延长的导通通道器件更快。此外，本发明包括具有高介电常数值（K）的电介质层以延长器件的使用寿命。轻掺杂漏极区域通过保护栅极免受“热电子注入”的类似地保留了IGFET的完整性。该方法和结构提供IGFET具有更高的性能，而不会影响IGFET的可靠性或寿命。

30. 发明授权

US5959337A Air gap spacer formation for high performance MOSFETs 失效
标题翻译：用于高性能MOSFET的气隙间隔物形成
公开(公告)号：US5959337A
公开(公告)日：1999-09-28
申请号：US175193
申请日：1998-10-20
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/336 , H01L29/78 , H07L29/78
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/66598 , H01L29/7833
摘要： A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate. An interlevel dielectric is deposited to a level above the gate conductor across the semiconductor topography such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the gate conductor, and the interlevel dielectric is planarized to a level substantially coplanar with an upper surface of the masking structure. In an alternative embodiment, a refractory metal is deposited across an upper surface of the masking structure and across the source/drain implant areas subsequent to forming said source/drain implant areas. The refractory metal is heated to form a metal silicide overlying the source/drain implant areas and residual refractory metal is removed from above the masking structure. In yet another alternative embodiment, a single high-energy ion implant is used to simultaneously form the source/drain implant area and the lightly doped drain implant area following removal of select portions of the gate conductors.
摘要翻译：提供一种形成晶体管的方法，其中集成电路采用的栅极导体和相邻结构之间的电容耦合减小。根据实施例，栅极导体在半导体衬底之上介电间隔开，并且掩模结构布置在栅极导体的上表面上。执行与掩模结构的相对的侧向侧壁自对准的源极/漏极注入以在衬底内形成源极/漏极注入区域。选择栅极导体的部分被去除，使得掩模结构的相对端延伸超过栅极导体的相对的侧壁表面。执行与窄化栅极导体的相对侧壁表面自对准的轻掺杂漏极注入，以在衬底内形成轻掺杂的漏极注入区域。跨越半导体拓扑结构的层间电介质沉积到栅极导体上方的一个电平，使得气隙横向邻近栅极导体的相对的侧壁表面形成，并且层间电介质平坦化到基本上与平面的共面平面掩蔽结构。在替代实施例中，在形成所述源极/漏极注入区域之后，跨越掩模结构的上表面并横跨源极/漏极注入区域沉积难熔金属。难熔金属被加热以形成覆盖在源极/漏极注入区域上的金属硅化物，并且从掩蔽结构上方除去残留的难熔金属。在另一替代实施例中，在去除栅极导体的选择部分之后，单个高能离子注入用于同时形成源极/漏极注入区域和轻掺杂漏极注入区域。

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