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1. 发明授权

US07315765B1 Automated control thread determination based upon post-process consideration 有权
标题翻译：基于后处理考虑的自动控制线程确定
公开(公告)号：US07315765B1
公开(公告)日：2008-01-01
申请号：US11192691
申请日：2005-07-29
申请人： Alan Grosvenor Ranft , Daniel Kadosh
发明人： Alan Grosvenor Ranft , Daniel Kadosh
IPC分类号： G06F19/00
CPC分类号： G05B19/404 , G05B19/4187 , G05B2219/32297 , G05B2219/45031 , Y02P90/205
摘要： A method, apparatus, and a system for determining a control thread based upon a process result are provided. At least one post-process parameter is received. The post parameter relates to a first workpiece upon which a plurality of processes have been performed by a plurality of processing tools. A combination of at least a portion of the plurality of processing tools is selected based upon the post-process parameter.
摘要翻译：提供了一种基于处理结果来确定控制线程的方法，装置和系统。接收至少一个后处理参数。后参数涉及由多个处理工具执行多个处理的第一工件。基于后处理参数来选择多个处理工具的至少一部分的组合。

2. 发明授权

US07248939B1 Method and apparatus for multivariate fault detection and classification 有权
标题翻译：多变量故障检测和分类方法与装置
公开(公告)号：US07248939B1
公开(公告)日：2007-07-24
申请号：US11035276
申请日：2005-01-13
申请人： Kevin Andrew Chamness , Daniel Kadosh , Gregory A. Cherry , Jason Williams
发明人： Kevin Andrew Chamness , Daniel Kadosh , Gregory A. Cherry , Jason Williams
IPC分类号： G06F19/00
CPC分类号： H01L21/67288 , H01L21/67276
摘要： The present invention provides a method and apparatus for multivariate fault identification and classification. The method includes accessing data indicative of a plurality of physical parameters associated with a plurality of processed semiconductor wafers and providing at least one summary report including information indicative of at least one univariate representation of the accessed data and at least one multivariate representation of the accessed data.
摘要翻译：本发明提供了一种用于多变量故障识别和分类的方法和装置。该方法包括访问指示与多个处理的半导体晶片相关联的多个物理参数的数据，并且提供包括指示所访问数据的至少一个单变量表示的信息的至少一个概要报告和所访问数据的至少一个多变量表示。

3. 发明授权

US06403979B1 Test structure for measuring effective channel length of a transistor 失效
标题翻译：用于测量晶体管有效沟道长度的测试结构
公开(公告)号：US06403979B1
公开(公告)日：2002-06-11
申请号：US09780834
申请日：2001-02-09
申请人： Daniel Kadosh , Jon D. Cheek
发明人： Daniel Kadosh , Jon D. Cheek
IPC分类号： H01L2358
CPC分类号： H01L22/34
摘要： A test structure for use in determining an effective channel length of a transistor is disclosed herein. The test structure comprises a first resistor comprised of a first doped region formed in a semiconducting substrate between a first pair of spaced-apart structures positioned above the substrate, the first resistor having a first width defined by the spacing between the first pair of structures, a second resistor comprised of a second doped region formed in the substrate between a second pair of spaced-apart structures positioned above the substrate, the second resistor having a second width defined by the spacing between the second pair of structures, the second width being greater than the first width, and a plurality of conductive contacts electrically coupled to each of the first and second doped regions. The method disclosed herein comprises determining the extent of lateral encroachment of the doped regions under the structures based upon the following formula: &Dgr;w=(R1W1 −R2W2)/(R1−R2). The effective channel length of the transistor may be determined by subtracting the &Dgr;w value from the length of the gate electrode.
摘要翻译：本文公开了用于确定晶体管的有效沟道长度的测试结构。测试结构包括第一电阻器，该第一电阻器由形成在半导体衬底中的第一掺杂区域构成，位于衬底上方的第一对隔开的结构之间，第一电阻器具有由第一对结构之间的间隔限定的第一宽度，第二电阻器，包括形成在衬底中的位于衬底上方的第二对隔开的结构之间的第二掺杂区域，第二电阻器具有由第二对结构之间的间隔限定的第二宽度，第二宽度更大并且多个导电触点电耦合到第一和第二掺杂区域中的每一个。本文公开的方法包括基于以下公式确定结构下的掺杂区域的横向侵入的程度：DELTAw =（R1W1-R2W2）/（R1-R2）。可以通过从栅电极的长度减去DELTAw值来确定晶体管的有效沟道长度。

4. 发明授权

US06232637B1 Semiconductor fabrication having multi-level transistors and high density interconnect therebetween 有权
标题翻译：具有多电平晶体管和其间的高密度互连的半导体制造
公开(公告)号：US06232637B1
公开(公告)日：2001-05-15
申请号：US09249954
申请日：1999-02-12
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L31036
CPC分类号： H01L27/0688 , H01L21/8221
摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.
摘要翻译：提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构。升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。提供晶体管，其包括在一对结之间间隔开的栅极导体。在晶体管两端沉积初级层间电介质。在初级层间电介质的上表面的选择部分内形成多晶硅结构。多晶硅结构是距离晶体管的上方和横向距离之间的间隔距离。将掺杂剂注入到多晶硅结构中。次级层间电介质沉积在初级层间电介质和掺杂多晶硅结构之间。选择部分初级和次级层间电介质然后被去除以暴露出一个结点，并且掺杂多晶硅结构的一部分布置在该结附近。通过在去除的部分内沉积导电材料，在结和多晶硅结构之间连续地形成互连。

5. 发明授权

US06218251B1 Asymmetrical IGFET devices with spacers formed by HDP techniques 有权
标题翻译：通过HDP技术形成间隔物的非对称IGFET器件
公开(公告)号：US06218251B1
公开(公告)日：2001-04-17
申请号：US09187894
申请日：1998-11-06
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L29/6653 , H01L29/66659 , H01L29/7835
摘要： In an IGFET device having at least one source/drain region with a lightly-doped sub-region proximate a channel region, the source/drain regions are formed by first implanting ions with parameters to form lightly-doped source/drain regions. A high density plasma deposition provides at least one spacer having preselected characteristics. As a result of the spacer characteristics, an ion implantation with parameters to form normally-doped source/drain regions is shadowed by the spacer. A portion of the source/drain region shadowed by the spacer results in a lightly-doped source/drain sub-region proximate the channel region. According to a second embodiment of the invention, the ion implantation resulting in the lightly-doped source/drain regions is eliminated. Instead, the spacer(s) formed by the high density plasma deposition and subsequent etching process only partially shadows the ion implantation that would otherwise result in normal doping of the source/drain regions. The parameters of the spacer(s) resulting from the high density plasma deposition and subsequent etching process result in a lightly-doped source/drain sub-region proximate the channel region. The shadowing of the spacer decreases with distance from the gate structure and results in a normal doping level for the portion of the source/drain terminal not shadowed by the spacer.
摘要翻译：在具有至少一个具有靠近沟道区的轻掺杂子区域的源极/漏极区域的IGFET器件中，通过首先用参数注入离子以形成轻掺杂的源极/漏极区域来形成源极/漏极区域。高密度等离子体沉积提供至少一个具有预选特性的间隔物。作为间隔物特性的结果，具有形成常态掺杂源极/漏极区域的参数的离子注入被间隔物遮蔽。由间隔物遮蔽的源极/漏极区域的一部分导致靠近沟道区域的轻掺杂源极/漏极子区域。根据本发明的第二实施例，消除了导致轻掺杂源/漏区的离子注入。替代地，通过高密度等离子体沉积和随后的蚀刻工艺形成的间隔物仅部分地影响否则将导致源/漏区的正常掺杂的离子注入。由高密度等离子体沉积和随后的蚀刻工艺产生的间隔物的参数导致靠近沟道区的轻掺杂的源极/漏极子区域。间隔物的阴影随着与栅极结构的距离而减小，并且导致源极/漏极端子的未被间隔物遮蔽的部分的正常掺杂水平。

6. 发明授权

US06172381B2 Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall 有权
标题翻译：源极/漏极结区域在侧壁间隔物和蚀刻的侧壁之间自对准
公开(公告)号：US06172381B2
公开(公告)日：2001-01-09
申请号：US09219146
申请日：1998-12-22
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L2702
CPC分类号： H01L21/76897 , H01L21/76838 , H01L21/8221 , H01L23/5226 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer. The second transistor has a pair of implant regions spaced from each other by a gate conductor and a pair of oxide spacers arranged on opposed sidewall surfaces of the gate conductor. Part of the polysilicon layer is removed such that polysilicon only extends under the gate conductor and terminates a pre-defined distance from each of the pair of oxide spacers. A pair of junctions remain for the second transistor that are defined between an etched lateral edge and an oxide spacer. A second interlevel dielectric may be deposited across the second transistor and exposed areas of the primary interlevel dielectric to isolate the transistor from other active devices.
摘要翻译：提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构并将其与位于同一高架平面中的另一多晶硅结构隔离。升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。提供了第一晶体管，其设置在硅基衬底上并且位于硅基衬底内。在晶体管和衬底两端沉积初级层间电介质。然后可以将多晶硅沉积在初级层间电介质上并使用离子注入进行掺杂。可以在多晶硅层的一部分上形成第二晶体管。第二晶体管具有通过栅极导体和布置在栅极导体的相对的侧壁表面上的一对氧化物隔离物彼此隔开的一对注入区域。去除多晶硅层的一部分，使得多晶硅仅在栅极导体下方延伸并且终止与一对氧化物间隔物中的每一个的预定距离。在蚀刻的侧边缘和氧化物间隔物之间限定的第二晶体管保留一对结。可以跨越第二晶体管和初级层间电介质的暴露区域沉积第二层间电介质以将晶体管与其它有源器件隔离。

7. 发明授权

US6137145A Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon 有权
标题翻译：半导体形貌包括集成了多层多晶硅层的集成电路栅极导体
公开(公告)号：US6137145A
公开(公告)日：2000-10-24
申请号：US237773
申请日：1999-01-26
申请人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
发明人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
IPC分类号： H01L21/8234 , H01K29/76
CPC分类号： H01L21/82345
摘要： A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal. The first gate conductor may be doped with a first dopant that has a lower diffusion rate through polysilicon than a second dopant with which the second gate conductor is doped. The second polysilicon layer portion of the second gate conductor is substantially free of implanted dopants.
摘要翻译：提供包括并入双多晶硅层的集成电路栅极导体的半导体形貌。半导体形貌包括半导体衬底。第一栅极导体布置在第一栅极电介质上并位于半导体衬底之上，并且第二栅极导体布置在第二栅极电介质上并位于半导体衬底之上。半导体衬底可以包含通过场区域与第二有源区域横向分离的第一有源区域。第一栅极导体可以布置在第一有源区内，并且第二栅极导体可以布置在第二有源区内。每个栅极导体优选地包括布置在第一多晶硅层部分上的第二多晶硅层部分。第一栅极导体和第二栅极导体的厚度优选相等。第一栅极导体可以掺杂有第一掺杂剂，其通过多晶硅具有比掺杂第二栅极导体的第二掺杂物更低的扩散速率。第二栅极导体的第二多晶硅层部分基本上没有注入的掺杂剂。

8. 发明授权

US06104069A Semiconductor device having an elevated active region formed in an oxide trench 有权
标题翻译：具有形成在氧化物沟槽中的升高的有源区的半导体器件
公开(公告)号：US06104069A
公开(公告)日：2000-08-15
申请号：US187462
申请日：1998-11-04
申请人： Michael Duane , Daniel Kadosh , Mark I. Gardner
发明人： Michael Duane , Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768 , H01L29/417 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66568 , H01L21/76877 , H01L29/41725 , H01L29/41733 , H01L29/66575 , H01L29/7833 , H01L21/2257 , H01L29/665 , Y10S257/90
摘要： A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.
摘要翻译：公开了一种用于形成具有升高的有源区的半导体器件的工艺。该工艺包括在半导体衬底上形成多个栅电极，并在栅电极上设置厚氧化层。在厚的氧化物层中形成沟槽并填充有多晶硅材料。随后掺杂多晶硅材料以便在衬底的有源区上方形成升高的有源区。

9. 发明授权

US6097096A Metal attachment method and structure for attaching substrates at low temperatures 失效
标题翻译：用于在低温下安装基板的金属附着方法和结构
公开(公告)号：US6097096A
公开(公告)日：2000-08-01
申请号：US890377
申请日：1997-07-11
申请人： Mark I. Gardner , Fred Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred Hause , Daniel Kadosh
IPC分类号： H01L21/768 , H01L21/98 , H01L23/532 , H01L25/065 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/50 , H01L21/76801 , H01L21/76834 , H01L23/5329 , H01L24/80 , H01L25/0657 , H01L2224/05571 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06541 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3011
摘要： A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.
摘要翻译：高密度集成电路结构及其制造方法包括提供具有根据第一电路实现的半导体器件结构的第一硅衬底结构和设置在其顶表面上的金属层间线以及具有第二电路的第二硅衬底结构实施和设置在其顶表面上的金属层间线。第一衬底结构包括设置在金属层间线之间的平面化低K电介质和将金属层间线与低K电介质分开的保护涂层，第一硅衬底结构的金属层间线具有按顺序的熔融温度小于500℃的低K电介质，介电K值在2.0-3.8范围内。第二基板结构还包括布置在金属层间线之间的平坦化的低K电介质和将金属层间线与低K电介质隔开的保护涂层，金属层间线具有小于500°的熔融温度并且介电K值在2.0-3.8范围内的低K电介质。最后，第一衬底结构在第一和第二衬底结构的相应的金属层间线处被低温地结合到第二衬底结构。

10. 发明授权

US6075268A Ultra high density inverter using a stacked transistor arrangement 有权
标题翻译：使用堆叠晶体管布置的超高密度逆变器
公开(公告)号：US6075268A
公开(公告)日：2000-06-13
申请号：US188972
申请日：1998-11-10
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/822 , H01L27/06 , H01L29/76 , H01L23/02 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L27/0688 , H01L21/8221 , H01L2924/0002
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds the to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows formation of a high density inverter circuit hereof.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同级别的器件之间的高性能互连。互连配置在一个晶体管电平内的特征之间尽可能短，在另一个晶体管级内的特征。该互连方案通过在下级晶体管的栅极导体上形成上层晶体管的栅极导体来降低电阻率。或者，栅极导体可以是单个导电实体。为了将栅导体邻接在一起或形成单个栅极导体，上层晶体管相对于下层晶体管反相。除了反向共享栅极导体之外，多级晶体管制造工艺包括形成开口和填充这些开口以产生与上/下晶体管的结的互连。将一对堆叠晶体管的栅极导体和这些晶体管的连接特定结之间的互连允许形成其中的高密度反相器电路。

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