专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07504270B2 Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same 有权
标题翻译：量化由各种特征的制造引起的角圆化引起的变化的方法以及用于测试相同的结构的方法
公开(公告)号：US07504270B2
公开(公告)日：2009-03-17
申请号：US11425913
申请日：2006-06-22
申请人： David D. Wu , Mark W. Michael , Akif Sultan , Jingrong Zhou
发明人： David D. Wu , Mark W. Michael , Akif Sultan , Jingrong Zhou
IPC分类号： G10R31/26 , H01L21/66
CPC分类号： H01L22/34 , G03F7/70658 , H01L22/12
摘要： The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.
摘要翻译：本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果以确定制造性角落四舍五入对多个测试结构的性能的影响。

2. 发明授权

US07355201B2 Test structure for measuring electrical and dimensional characteristics 有权
标题翻译：用于测量电气和尺寸特性的测试结构
公开(公告)号：US07355201B2
公开(公告)日：2008-04-08
申请号：US11426723
申请日：2006-06-27
申请人： Jianhong Zhu , David D. Wu , Mark W. Michael
发明人： Jianhong Zhu , David D. Wu , Mark W. Michael
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , G01R31/2648
摘要： A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of fingers extending from the second base. At least a portion of the first and second pluralities of fingers are interleaved. The first pair of base nodes extend from the first base. The second pair of finger nodes extend from a first finger of the first plurality of fingers.
摘要翻译：测试结构包括第一和第二梳，至少第一对基本节点和第二对手指节点。第一梳子包括从第一基部延伸的第一基部和第一多个指状物。第二梳子包括从第二基部延伸的第二基部和第二多个指状物。第一和第二多个手指的至少一部分交错。第一对基本节点从第一个基地延伸。所述第二对手指节点从所述第一多个手指的第一手指延伸。

3. 发明授权

US06964875B1 Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance 失效
标题翻译：用于测量栅介质厚度和寄生电容的栅介质结构阵列
公开(公告)号：US06964875B1
公开(公告)日：2005-11-15
申请号：US10962582
申请日：2004-10-13
申请人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
发明人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
IPC分类号： H01L21/66 , H01L21/8234 , H01L23/544 , H01L27/08 , H01L29/76 , H01L31/119
CPC分类号： H01L22/34 , H01L21/823437 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.
摘要翻译：制造高可靠性和高性能超薄栅极电介质半导体器件需要精确确定栅极电介质厚度。具有超薄栅极介电层的大面积栅极介质电容器具有高栅极泄漏，这阻止了栅极电介质厚度的精确测量。较小面积的电介质电容器的栅极电介质厚度的精确测量受到较小面积电容器的相对大的寄生电容的阻碍。在晶片上形成第一和第二虚拟结构允许准确地确定栅极电介质厚度。形成基本上类似于栅极介电电容器的第一和第二虚拟结构，除了第一虚拟结构形成而没有电容器的第二电极，并且第二虚拟结构形成而没有电容器结构的第一电极。通过减去在第一和第二虚拟结构处测量的寄生电容来确定栅极介电电容器的电容，并因此确定厚度。

4. 发明授权

US06780776B1 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer 有权
标题翻译：氮化物偏移间隔物，通过使用多重再氧化层作为蚀刻停止层来最小化硅凹槽
公开(公告)号：US06780776B1
公开(公告)日：2004-08-24
申请号：US10023328
申请日：2001-12-20
申请人： Wen-Jie Qi , John G. Pellerin , William G. En , Mark W. Michael , Darin A. Chan
发明人： Wen-Jie Qi , John G. Pellerin , William G. En , Mark W. Michael , Darin A. Chan
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/31116 , H01L21/3185 , H01L29/6656
摘要： A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.
摘要翻译：形成半导体器件的方法在衬底上提供栅电极，并在衬底和栅电极上形成多晶硅再氧化层。氮化物层沉积在多晶硅再氧化层上并各向异性蚀刻。多晶硅再氧化层上的蚀刻停止，在栅电极上形成氮化物偏移间隔物。使用多晶硅再氧化层作为蚀刻停止层防止在氮化物层下方的硅衬底的气蚀，同时允许形成偏移间隔物。

5. 发明授权

US06326298B1 Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 有权
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US06326298B1
公开(公告)日：2001-12-04
申请号：US09513293
申请日：2000-02-25
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L214763
CPC分类号： H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

6. 发明授权

US06188114B1 Method of forming an insulated-gate field-effect transistor with metal spacers 有权
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US06188114B1
公开(公告)日：2001-02-13
申请号：US09204016
申请日：1998-12-01
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31119
CPC分类号： H01L29/41783 , H01L29/41775 , H01L29/66575 , H01L29/6659
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

7. 发明授权

US6166354A System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication 失效
标题翻译：用于半导体制造中退火的原位监测和控制的系统和装置
公开(公告)号：US6166354A
公开(公告)日：2000-12-26
申请号：US876381
申请日：1997-06-16
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： C30B31/12 , C30B31/18 , F27B5/14
CPC分类号： C30B31/18 , C30B31/12
摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.
摘要翻译：在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。监测表面光电压测量，检测退火时间，并控制所选择的过退火。执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。检测点也用于终止退火过程以最小化Dt。

8. 发明授权

US6153833A Integrated circuit having interconnect lines separated by a dielectric having a capping layer 有权
标题翻译：具有由具有封盖层的电介质隔开的互连线的集成电路
公开(公告)号：US6153833A
公开(公告)日：2000-11-28
申请号：US148098
申请日：1998-09-04
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H05K1/03
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。此外，层间和层间介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

9. 发明授权

US6150721A Integrated circuit which uses a damascene process for producing staggered interconnect lines 有权
标题翻译：集成电路，其使用镶嵌工艺来产生交错的互连线
公开(公告)号：US6150721A
公开(公告)日：2000-11-21
申请号：US132454
申请日：1998-08-11
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/768 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

10. 发明授权

US6146978A Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance 失效
标题翻译：集成电路具有耦合到具有源极/漏极区域的源极/漏极区域的层间互连重叠和减小的寄生电容
公开(公告)号：US6146978A
公开(公告)日：2000-11-14
申请号：US73639
申请日：1998-05-06
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/8238 , H01L21/44 , H01L21/4763 , H01L31/119
CPC分类号： H01L21/823871 , H01L21/76802 , H01L21/76895
摘要： An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.
摘要翻译：在通过隔离层打开的窗口中并通过蚀刻屏障形成层间互连，以露出电极表面和相邻隔离屏障。层间互连可以布置在底层电极的基本上全部的一部分上，例如绝缘栅场效应晶体管（IGFET）源/漏区表面。蚀刻屏障提供受控的蚀刻，以允许层间互连重叠在隔离屏障上，而不增加寄生电容，相对于传统的接触不对准。此外，消除重叠的关注允许通过层间互连增加源/漏区表面积的利用。此外，蚀刻屏障允许层间互连以多个电路器件的带状电极同时显示标称的任何衬底以互连互连漏电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式