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1. 发明授权

US5945718A Self-aligned metal-oxide-compound semiconductor device and method of fabrication 失效
标题翻译：自对准金属氧化物半导体器件及其制造方法
公开(公告)号：US5945718A
公开(公告)日：1999-08-31
申请号：US22593
申请日：1998-02-12
申请人： Matthias Passlack , Jonathan Kwadwo Abrokwah , Zhiyi Yu
发明人： Matthias Passlack , Jonathan Kwadwo Abrokwah , Zhiyi Yu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H07L29/78
CPC分类号： H01L29/517 , H01L21/28158 , H01L29/66522
摘要： A self-aligned enhancement mode metal-oxide-compound semiconductor FET (10) includes a stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14) positioned on upper surface (16) of a compound semiconductor wafer structure (13). The stoichiometric Ga.sub.2 O.sub.3 layer forms an atomically abrupt interface with the compound semiconductor wafer structure. A refractory metal gate electrode (17) is positioned on upper surface (18) of the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14). The refractory metal is stable on the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22).
摘要翻译：自对准增强型金属氧化物半导体FET（10）包括位于化合物半导体晶片结构（13）的上表面（16）上的化学计量的Ga 2 O 3栅极氧化物层（14）。化学计量的Ga 2 O 3层与化合物半导体晶片结构形成原子突变的界面。难熔金属栅电极（17）位于化学计量的Ga 2 O 3栅极氧化物层（14）的上表面（18）上。难熔金属在高温下在化学计量的Ga 2 O 3栅极氧化物层上是稳定的。自对准源极和漏极区以及源极和漏极接触（19,20）位于源极和漏极区域（21,22）上。

2. 发明授权

US5959337A Air gap spacer formation for high performance MOSFETs 失效
标题翻译：用于高性能MOSFET的气隙间隔物形成
公开(公告)号：US5959337A
公开(公告)日：1999-09-28
申请号：US175193
申请日：1998-10-20
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/336 , H01L29/78 , H07L29/78
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/66598 , H01L29/7833
摘要： A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate. An interlevel dielectric is deposited to a level above the gate conductor across the semiconductor topography such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the gate conductor, and the interlevel dielectric is planarized to a level substantially coplanar with an upper surface of the masking structure. In an alternative embodiment, a refractory metal is deposited across an upper surface of the masking structure and across the source/drain implant areas subsequent to forming said source/drain implant areas. The refractory metal is heated to form a metal silicide overlying the source/drain implant areas and residual refractory metal is removed from above the masking structure. In yet another alternative embodiment, a single high-energy ion implant is used to simultaneously form the source/drain implant area and the lightly doped drain implant area following removal of select portions of the gate conductors.
摘要翻译：提供一种形成晶体管的方法，其中集成电路采用的栅极导体和相邻结构之间的电容耦合减小。根据实施例，栅极导体在半导体衬底之上介电间隔开，并且掩模结构布置在栅极导体的上表面上。执行与掩模结构的相对的侧向侧壁自对准的源极/漏极注入以在衬底内形成源极/漏极注入区域。选择栅极导体的部分被去除，使得掩模结构的相对端延伸超过栅极导体的相对的侧壁表面。执行与窄化栅极导体的相对侧壁表面自对准的轻掺杂漏极注入，以在衬底内形成轻掺杂的漏极注入区域。跨越半导体拓扑结构的层间电介质沉积到栅极导体上方的一个电平，使得气隙横向邻近栅极导体的相对的侧壁表面形成，并且层间电介质平坦化到基本上与平面的共面平面掩蔽结构。在替代实施例中，在形成所述源极/漏极注入区域之后，跨越掩模结构的上表面并横跨源极/漏极注入区域沉积难熔金属。难熔金属被加热以形成覆盖在源极/漏极注入区域上的金属硅化物，并且从掩蔽结构上方除去残留的难熔金属。在另一替代实施例中，在去除栅极导体的选择部分之后，单个高能离子注入用于同时形成源极/漏极注入区域和轻掺杂漏极注入区域。

3. 发明授权

US6153908A Buried-gate semiconductor device with improved level of integration 失效
标题翻译：埋地半导体器件具有提高的集成度
公开(公告)号：US6153908A
公开(公告)日：2000-11-28
申请号：US305212
申请日：1999-05-05
申请人： Hiroaki Ohkubo
发明人： Hiroaki Ohkubo
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/768 , H01L29/78 , H07L29/78
CPC分类号： H01L29/66621 , H01L21/32051 , H01L21/76802 , H01L21/76831 , H01L29/7834
摘要： In a semiconductor device in which a source and a drain are formed on both sides of a buried gate provided in a trench, metal wires for the source and the drain are provided above the source and drain, via an intervening interlayer insulation film, a wire for a gate being provided so as to be sandwiched between the source and drain wires, this being formed on the same level of interconnect layers as the source and drain wires and being formed over the gate.
摘要翻译：在设置在沟槽中的掩埋栅极的两侧上形成源极和漏极的半导体器件中，用于源极和漏极的金属线通过中间层间绝缘膜，导线和漏极设置在源极和漏极之上，为了将栅极设置成夹在源极和漏极之间的栅极，它们形成在与源极和漏极导线相同的互连层上并形成在栅极上。

4. 发明授权

US5959336A Decoder circuit with short channel depletion transistors 失效
标题翻译：具有短沟道耗尽晶体管的解码器电路
公开(公告)号：US5959336A
公开(公告)日：1999-09-28
申请号：US702846
申请日：1996-08-26
申请人： Radu M. Barsan
发明人： Radu M. Barsan
IPC分类号： H07L29/78
CPC分类号： H01L27/0883 , G11C8/08 , G11C8/10 , H01L27/0207 , H03K19/17728 , Y10S257/907
摘要： A decoder circuit formed on an integrated circuit substrate including at least one short channel depletion transistor having a low resistance path formed between the source and the drain regions. The low resistance path is provided by an implant into the channel region that forms a depletion channel wherein the channel region has a length less than a length of a channel region of transistors in the decoder circuit that handle input/output voltage levels for the decoder circuit.
摘要翻译：一种形成在集成电路衬底上的解码器电路，包括至少一个短沟道耗尽晶体管，其具有形成在源区和漏区之间的低电阻路径。低电阻路径由注入器提供到形成耗尽沟道的沟道区中，其中沟道区具有小于解码器电路中处理解码器电路的输入/输出电压电平的晶体管的沟道区的长度的长度。

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