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1. 发明授权

US06104069A Semiconductor device having an elevated active region formed in an oxide trench 有权
标题翻译：具有形成在氧化物沟槽中的升高的有源区的半导体器件
公开(公告)号：US06104069A
公开(公告)日：2000-08-15
申请号：US187462
申请日：1998-11-04
申请人： Michael Duane , Daniel Kadosh , Mark I. Gardner
发明人： Michael Duane , Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768 , H01L29/417 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66568 , H01L21/76877 , H01L29/41725 , H01L29/41733 , H01L29/66575 , H01L29/7833 , H01L21/2257 , H01L29/665 , Y10S257/90
摘要： A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.
摘要翻译：公开了一种用于形成具有升高的有源区的半导体器件的工艺。该工艺包括在半导体衬底上形成多个栅电极，并在栅电极上设置厚氧化层。在厚的氧化物层中形成沟槽并填充有多晶硅材料。随后掺杂多晶硅材料以便在衬底的有源区上方形成升高的有源区。

2. 发明授权

US6004849A Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source 失效
标题翻译：在漏极上制造具有硅化物接触的不对称IGFET的方法，而不在源极上具有硅化物接触
公开(公告)号：US6004849A
公开(公告)日：1999-12-21
申请号：US911745
申请日：1997-08-15
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/28114 , H01L29/665 , H01L29/7835
摘要： A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain region, forming a gate insulator on the active region, forming a gate on the gate insulator and over the active region, implanting arsenic into the active region to provide a greater concentration of arsenic in the source region than in the drain region, growing an oxide layer over the active region, wherein the oxide layer has a greater thickness over the source region than over the drain region due to the greater concentration of arsenic in the source region than in the drain region, forming a source in the source region and a drain in the drain region, depositing a refractory metal over the gate, the source, the drain, and the oxide layer, and reacting the refractory metal with the drain without reacting the refractory metal with the source, thereby forming a silicide contact on the drain without forming a silicide contact on the source. Advantageously, the IGFET has low source-drain resistance, shallow channel junctions, and an LDD that reduces hot carrier effects.
摘要翻译：公开了制造不对称IGFET的方法。该方法包括提供具有有源区的半导体衬底，其中有源区包括源极区和漏极区，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上方形成栅极，将砷注入所述有源区域在所述源极区域中提供比在所述源极区域中更大的砷浓度，在所述有源区域上生长氧化物层，其中所述氧化物层在所述源极区域上比在所述漏极区域上的厚度大于所述漏极区域上的厚度在源极区域中的砷浓度比漏极区域中的砷浓度高，在源极区域形成源极，在漏极区域形成漏极，在栅极，源极，漏极和氧化物层上沉积难熔金属，并使具有漏极的难熔金属，而不使难熔金属与源极反应，从而在漏极上形成硅化物接触，而不在源上形成硅化物接触。有利地，IGFET具有低源极 - 漏极电阻，浅沟道结和降低热载流子效应的LDD。

3. 发明授权

US5834350A Elevated transistor fabrication technique 失效
公开(公告)号：US5834350A
公开(公告)日：1998-11-10
申请号：US873116
申请日：1997-06-11
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/822 , H01L27/06 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

4. 发明授权

US6027978A Method of making an IGFET with a non-uniform lateral doping profile in the channel region 失效
标题翻译：在通道区域中制造具有不均匀横向掺杂分布的IGFET的方法
公开(公告)号：US6027978A
公开(公告)日：2000-02-22
申请号：US787036
申请日：1997-01-28
申请人： Mark I. Gardner , Michael Duane , Daniel Kadosh
发明人： Mark I. Gardner , Michael Duane , Daniel Kadosh
IPC分类号： H01L21/8234 , H01L29/10 , H01L21/336
CPC分类号： H01L29/1045 , H01L21/823412
摘要： A method of making an IGFET with a selectively doped channel region is disclosed. The method includes providing a semiconductor substrate with a device region, forming a gate over the device region, forming a masking layer that partially covers the gate and the device region, implanting a dopant into portions of the gate and the device region outside the gate that are not covered by the masking layer, transferring the dopant through the uncovered portion of the gate into a portion of an underlying channel region in the device region, thereby providing the channel region with a non-uniform lateral doping profile and adjusting a threshold voltage, and forming a source and a drain in the device region. The dopant can be implanted through the portion of the gate into the portion of the channel region, or alternatively, the dopant can be diffused from the portion of the gate into the portion of the channel region. In addition, the dopant can be the same conductivity type as the channel region, thereby increasing the dopant concentration of the portion of the channel region and adjusting the threshold voltage away from zero, or the dopant can be opposite conductivity type as the channel region, thereby decreasing the dopant concentration of the portion of the channel region and adjusting the threshold voltage towards zero. Preferably, the gate is polysilicon and the masking layer is photoresist. Advantageously, the invention is well-suited for adjusting the threshold voltage, and therefore the drive current, leakage current and speed, of selected IGFETs, so that the fastest IGFETs with the highest leakage currents can be placed in critical speed paths such as common lines in SRAM arrays.
摘要翻译：公开了一种制造具有选择性掺杂沟道区域的IGFET的方法。该方法包括提供具有器件区域的半导体衬底，在器件区域上形成栅极，形成部分地覆盖栅极和器件区域的掩模层，将掺杂剂注入到栅极外部的栅极和器件区域的部分，不被掩蔽层覆盖，将掺杂剂通过栅极的未覆盖部分转移到器件区域中的下游沟道区域的一部分中，从而为沟道区域提供非均匀的横向掺杂分布并调整阈值电压，以及在器件区域中形成源极和漏极。掺杂剂可以通过栅极的一部分注入到沟道区的部分中，或者，掺杂剂可以从栅极的一部分扩散到沟道区的部分。此外，掺杂剂可以是与沟道区相同的导电类型，从而增加沟道区的一部分的掺杂浓度，并将阈值电压调至零，或掺杂剂可以与沟道区相反的导电类型，从而降低沟道区的部分的掺杂剂浓度并将阈值电压调至零。优选地，栅极是多晶硅，掩模层是光致抗蚀剂。有利地，本发明非常适合于调整所选IGFET的阈值电压，因此调节驱动电流，泄漏电流和速度，使得具有最高漏电流的最快的IGFET可被放置在诸如公用线路的临界速度路径在SRAM阵列中。

5. 发明授权

US5898189A Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method 失效
标题翻译：集成电路包括氧化物隔离的局部衬底和标准硅衬底及其制造方法
公开(公告)号：US5898189A
公开(公告)日：1999-04-27
申请号：US905614
申请日：1997-08-04
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L29/76 , H01L21/263 , H01L29/04
CPC分类号： H01L27/0922 , H01L21/8221 , H01L27/0688
摘要： A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer. The median oxide isolation layer is patterned and etched according to a localized oxide isolation mask in a configuration determined by the position of transistors in the base-level transistor formation and by the planned position of transistors, that are not yet formed, in an overlying elevated substrate level. The median oxide isolation layer is patterned and etched in a configuration so that isolation is achieved in a predetermined manner, for example, on an individual transistor basis, a transistor group basis, or the like. The resulting electronic integrated circuit structure is used for high speed circuit applications due to high packing densities and small distances between devices.
摘要翻译：制造了多维晶体管结构，其包括形成晶体管的基极晶体管基板。形成了一个升高的衬底，覆盖着基极晶体管，并且在升高的衬底下方的局部区域中形成氧化物隔离层，但覆盖在基极晶体管衬底上。在衬底晶片上形成多个晶体管，以形成基极晶体管结构。层叠电介质（ILD）层沉积在基极晶体管结构之上。覆盖ILD层，通过第一多晶硅层的沉积，氧化物隔离层的沉积和第二多晶硅层的沉积形成“三明治”结构。根据局部氧化物隔离掩模对中间氧化物隔离层进行构图和蚀刻，该隔离掩模的形状由基极晶体管形成中的晶体管的位置和尚未形成的晶体管的预定位置确定底物水平。对中间氧化物隔离层进行图案化和蚀刻，以使得以预定的方式实现隔离，例如基于单个晶体管，基于晶体管组等。所得的电子集成电路结构由于高封装密度和器件之间的距离小而用于高速电路应用。

6. 发明授权

US5885761A Semiconductor device having an elevated active region formed from a thick polysilicon layer and method of manufacture thereof 失效
标题翻译：具有由厚多晶硅层形成的升高的有源区的半导体器件及其制造方法
公开(公告)号：US5885761A
公开(公告)日：1999-03-23
申请号：US780705
申请日：1997-01-08
申请人： Michael Duane , Daniel Kadosh , Mark I. Gardner
发明人： Michael Duane , Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/225 , H01L21/336 , H01L29/417 , H01L21/22 , H01L21/38 , H01L21/4763
CPC分类号： H01L29/66575 , H01L29/41775 , H01L29/41783 , H01L29/6659 , H01L21/2257 , H01L29/665
摘要： A semiconductor device and process for manufacture thereof is disclosed in which an elevated, active polysilicon region is formed by forming a gate electrode/nitride layer structure on a surface of a semiconductor substrate with spacers formed on adjacent walls to define an active region of the substrate. A thick polysilicon layer is formed over the resultant structure and then planarized leaving a portion of the polysilicon layer above the active region of the substrate. The remaining portion is doped to form an elevated active region.
摘要翻译：公开了一种半导体器件及其制造方法，其中通过在半导体衬底的表面上形成栅极/氮化物层结构形成升高的活性多晶硅区域，其中间隔物形成在相邻的壁上以限定衬底的有源区。在所得结构上形成厚的多晶硅层，然后平坦化，留下多晶硅层的一部分在衬底的有源区上方。剩余的部分被掺杂以形成升高的有源区。

7. 发明授权

US06420730B1 Elevated transistor fabrication technique 有权
标题翻译：高架晶体管制造技术
公开(公告)号：US06420730B1
公开(公告)日：2002-07-16
申请号：US09591871
申请日：2000-06-12
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L2976
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.
摘要翻译：在第一晶体管之上形成间隔距离的第二晶体管。首先在第一半导体衬底和第一晶体管的上表面上沉积层间电介质。然后，优选地包括多晶硅的第二半导体衬底形成层间电介质。然后在第二半导体衬底的上表面上形成第二晶体管。第二晶体管是在第一晶体管之上的间隔距离。两个晶体管是横向距离，其小于通过晶片的上表面上的晶体管的常规制造可以实现的距离。晶体管更紧密地封装，这导致每个晶片产生的器件数量的增加。

8. 发明授权

US6104064A Asymmetrical transistor structure 有权
标题翻译：不对称晶体管结构
公开(公告)号：US6104064A
公开(公告)日：2000-08-15
申请号：US306508
申请日：1999-05-06
申请人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
发明人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28211 , H01L21/28176 , H01L29/66659 , H01L29/7835
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

9. 发明授权

US6075258A Elevated transistor fabrication technique 有权
公开(公告)号：US6075258A
公开(公告)日：2000-06-13
申请号：US136177
申请日：1998-08-19
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/822 , H01L27/06 , H01L29/76
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

10. 发明授权

US6027964A Method of making an IGFET with a selectively doped gate in combination with a protected resistor 失效
标题翻译：制造具有选择性掺杂栅极的IGFET与保护电阻器组合的方法
公开(公告)号：US6027964A
公开(公告)日：2000-02-22
申请号：US905681
申请日：1997-08-04
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/02 , H01L21/266 , H01L21/336 , H01L27/06 , H01L21/8234
CPC分类号： H01L28/20 , H01L21/266 , H01L27/0629 , H01L29/66659
摘要： A method of making an IGFET with a selectively doped gate in combination with a protected resistor includes the steps of providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the active region and the resistor region, forming a masking layer over the insulating layer that includes an opening above a first portion of the gate and covers the resistor region and a second portion of the gate, applying an etch using the masking layer as an etch mask to remove the insulating layer above the first portion of the gate so that an unetched portion of the insulating layer forms a gate-protect insulator over the second portion of the gate and another unetched portion of the insulating layer forms a resistor-protect insulator over the diffused resistor, and forming a source and a drain in the active region including at least partially doping the source and the drain during a doping step that provides more doping for the first portion of the gate than for the second portion of the gate after forming the masking layer. In this manner, the masking layer can provide both an etch mask for the resistor-protect insulator and an implant mask for selectively doping the gate.
摘要翻译：制造具有选择性掺杂栅极的IGFET与受保护电阻器组合的方法包括以下步骤：为半导体衬底提供有源区域和电阻器区域，在有源区域上形成栅极，在电阻器区域中形成扩散电阻器在所述有源区和所述电阻区上方形成绝缘层，在所述绝缘层上形成掩模层，所述绝缘层包括在所述栅极的第一部分上方的开口，并且覆盖所述电阻器区域和所述栅极的第二部分，使用掩模层作为蚀刻掩模，以去除栅极的第一部分之上的绝缘层，使得绝缘层的未蚀刻部分在栅极的第二部分上形成栅极保护绝缘体，并且形成绝缘层的另一个未蚀刻部分在所述扩散电阻器上方的电阻保护绝缘体，以及在所述有源区域中形成至少部分掺杂所述酸的源极和漏极在掺杂步骤中，在形成掩模层之后，栅极的第一部分比栅极的第二部分提供更多的掺杂。以这种方式，掩模层可以提供用于电阻器保护绝缘体的蚀刻掩模和用于选择性地掺杂栅极的注入掩模。

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