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1. 发明授权

US07179745B1 Method for offsetting a silicide process from a gate electrode of a semiconductor device 失效
标题翻译：将硅化物工艺与半导体器件的栅电极相抵消的方法
公开(公告)号：US07179745B1
公开(公告)日：2007-02-20
申请号：US10860100
申请日：2004-06-04
申请人： Andrew M. Waite , Jon D. Cheek , David Brown
发明人： Andrew M. Waite , Jon D. Cheek , David Brown
IPC分类号： H01L21/311
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/66772
摘要： A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.
摘要翻译：一种用于在具有多晶硅栅电极，衬底中的源极和漏极区域以及衬底中的源极和漏极延伸部分的半导体器件上偏移硅化物的方法，在多晶硅栅电极的侧壁上采用氮化钛侧壁间隔物。氮化钛侧壁间隔物防止了在氧化过程中在源极和漏极延伸部分顶部的硅化物生长。然后通过蚀刻工艺去除氮化钛侧壁间隔物，该蚀刻工艺不蚀刻在源极和漏极区域以及多晶硅栅极电极中形成的硅化物区域。在移除氮化钛侧壁间隔物之后，可以将低k层间介电层或应力衬垫沉积在器件的顶部以增强器件性能。

2. 发明授权

US06720227B1 Method of forming source/drain regions in a semiconductor device 失效
标题翻译：在半导体器件中形成源/漏区的方法
公开(公告)号：US06720227B1
公开(公告)日：2004-04-13
申请号：US10059615
申请日：2002-01-29
申请人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
发明人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/7833
摘要： A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.
摘要翻译：提供了一种在半导体器件中形成源极/漏极区域的方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，通过至少执行以下步骤在衬底中邻近栅电极形成源极/漏极区：执行两个离子注入工艺以形成用于并且执行第三离子注入工艺以进一步形成用于该器件的源极/漏极区域。本发明可以使用各种N型和P型掺杂剂原子，例如砷，磷，硼和二氟化硼。

3. 发明授权

US06426262B1 Method of analyzing the effects of shadowing of angled halo implants 失效
标题翻译：分析角度晕轮植入物阴影效应的方法
公开(公告)号：US06426262B1
公开(公告)日：2002-07-30
申请号：US09644735
申请日：2000-08-23
申请人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
发明人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
IPC分类号： H01L218236
CPC分类号： H01L29/66492 , H01L21/26586
摘要： The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.
摘要翻译：本发明涉及一种包括形成多个晶体管的方法，每个晶体管具有至少一个栅电极，并且在晶体管中形成晕圈注入区，同时改变光晕注入角，掩模层高度和屏蔽层与晶体管的栅电极的横向偏移。该方法还包括确定晶体管中的至少一些晶体管的电性能特征，其中，所述卤素注入角，掩模层高度和掩模层的横向偏移中的至少一个不同，以及将所确定的电性能特性晶体管。

4. 发明授权

US06406964B1 Method of controlling junction recesses in a semiconductor device 有权
标题翻译：控制半导体器件中的接合凹部的方法
公开(公告)号：US06406964B1
公开(公告)日：2002-06-18
申请号：US09704008
申请日：2000-11-01
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/7833
摘要： The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.
摘要翻译：本发明涉及一种形成晶体管的方法。在一个实施例中，所述方法包括提供衬底，所述衬底被掺杂有第一类型的掺杂剂材料，在由所述隔离结构限定的所述衬底的有源区域中的所述衬底上形成晶体管，以及执行至少一个离子注入在与晶体管的栅电极相邻的衬底中注入掺杂剂原子的工艺。该方法还包括在晶体管上执行与第一类掺杂剂材料相反类型的掺杂剂材料的至少两个成角度的离子注入工艺，并执行至少一个退火工艺。

5. 发明授权

US06316302B1 Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant 有权
标题翻译：各向同性蚀刻要用于NMOS源极/漏极注入和PMOS LDD植入物的侧壁间隔物
公开(公告)号：US06316302B1
公开(公告)日：2001-11-13
申请号：US09604051
申请日：2000-06-26
申请人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
发明人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/823864 , H01L29/6656
摘要： A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
摘要翻译：提供了一种用于各向同性蚀刻侧壁间隔物对以减少每个侧壁间隔物的横向厚度的方法。在一个实施例中，第一和第二对侧壁间隔件同时形成在相应的第一和第二栅极导体的相对的侧壁表面上。第一和第二栅极导体分别在半导体衬底的隔离的第一和第二有源区域上横向间隔开。有利地，在形成PMOS晶体管的NMOS晶体管和LDD区域的源极和漏极区域期间，单个侧壁间隔物对被用作掩模结构。也就是说，在减少侧壁间隔物的横向厚度之前，n +源极/漏极（“S / D”）植入物在第一对侧壁间隔物的外侧边缘上自对准。然而，在间隔物厚度减小之后，p-LDD植入物自对准到第二对侧壁间隔物的外侧边缘。因此，不需要在栅极导体的侧壁表面附近形成多对侧壁间隔件，以改变注入区域和后续集成电路的栅极导体之间的间隔。

6. 发明授权

US06180475B2 Transistor formation with local interconnect overetch immunity 有权
标题翻译：晶体管形成与局部互连overetch免疫
公开(公告)号：US06180475B2
公开(公告)日：2001-01-30
申请号：US09134702
申请日：1998-08-14
申请人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21336
CPC分类号： H01L21/76895 , H01L21/76224
摘要： An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.
摘要翻译：提供一种集成电路晶体管及其制造方法。晶体管由于局部互连沟槽的过蚀刻而抵抗结短路。该晶体管包括具有第一结的源极/漏极区域和位于有源区域的易于经过过渡接合短路现象的部分中比第一结点更深的第二结点。第二结通过通过掩模的离子注入建立，其被图案化以产生对应于有源区和局部互连沟槽的布局的相交的开口。使用该方法，仅在需要防止短路并且不妨碍晶体管性能的情况下才建立第二结。

7. 发明授权

US6124610A Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant 失效
标题翻译：各向同性蚀刻要用于NMOS源极/漏极注入和PMOS LDD植入物的侧壁间隔物
公开(公告)号：US6124610A
公开(公告)日：2000-09-26
申请号：US105872
申请日：1998-06-26
申请人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
发明人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/72
CPC分类号： H01L29/6659 , H01L21/823864 , H01L29/6656
摘要： A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n source/drain ("S/D") implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p.sup.- LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
摘要翻译：提供了一种用于各向同性蚀刻侧壁间隔物对以减少每个侧壁间隔物的横向厚度的方法。在一个实施例中，第一和第二对侧壁间隔件同时形成在相应的第一和第二栅极导体的相对的侧壁表面上。第一和第二栅极导体分别在半导体衬底的隔离的第一和第二有源区域上横向间隔开。有利地，在形成PMOS晶体管的NMOS晶体管和LDD区域的源极和漏极区域期间，单个侧壁间隔物对被用作掩模结构。也就是说，在减少侧壁间隔物的横向厚度之前，n源极/漏极（“S / D”）植入物在第一对侧壁间隔物的外侧边缘上自对准。然而，在间隔物厚度减小之后，p-LDD植入物自对准到第二对侧壁间隔物的外侧边缘。因此，不需要在栅极导体的侧壁表面附近形成多对侧壁间隔件，以改变注入区域和后续集成电路的栅极导体之间的间隔。

8. 发明授权

US5986283A Test structure for determining how lithographic patterning of a gate conductor affects transistor properties 失效
标题翻译：用于确定栅极导体的平版印刷图案如何影响晶体管特性的测试结构
公开(公告)号：US5986283A
公开(公告)日：1999-11-16
申请号：US30751
申请日：1998-02-25
申请人： John J. Bush , Jon D. Cheek , Mark I. Gardner
发明人： John J. Bush , Jon D. Cheek , Mark I. Gardner
IPC分类号： H01L21/66 , H01L23/58 , G01R31/26
CPC分类号： G03F7/70658 , H01L22/14 , H01L2924/0002
摘要： The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequence of gate conductors interposed above and between a respective sequence of source and drain regions. The test structure further includes a sequence of conductors which have been patterned from the same material as the gate conductors. The conductors are spaced an increasing distance from respective gate conductors. The gate conductors extend beyond the respective source and drain regions by varying distances or by the same distance. Lithographic patterning of the gate conductors and the conductors may result in the edges of the gate conductors and the conductors being substantially round and absent of sharp corners. Further, lithographic patterning may lead to a reduction in the lengths of the gate conductors and the conductors. The length of each gate conductor extends along the same axis as the length of the conductor nearest to the gate conductor.
摘要翻译：本发明有利地提供了一种测试结构和方法，用于确定与导体横向间隔开的晶体管栅极导体的平版印刷图案如何影响采用栅极导体的晶体管的操作。测试结构包括插入在源极和漏极区域的相应序列之间和之间的栅极导体序列。该测试结构进一步包括一系列导体，该导体序列由与栅极导体相同的材料构图。导体与相应的栅极导体间隔开增加的距离。栅极导体通过变化的距离或相同的距离延伸超过相应的源极和漏极区域。栅极导体和导体的平版印刷图案可能导致栅极导体和导体的边缘基本上圆形且不存在锐角。此外，光刻图案化可能导致栅极导体和导体的长度减小。每个栅极导体的长度沿与导体最接近的导体的长度相同的轴线延伸。

9. 发明授权

US5926693A Two level transistor formation for optimum silicon utilization 失效
标题翻译：用于最佳硅利用的两级晶体管形成
公开(公告)号：US5926693A
公开(公告)日：1999-07-20
申请号：US788376
申请日：1997-01-27
申请人： Mark I. Gardner , Fred N. Hause , Jon D. Cheek
发明人： Mark I. Gardner , Fred N. Hause , Jon D. Cheek
IPC分类号： H01L27/07 , H01L27/088 , H01L21/00
CPC分类号： H01L27/0705 , H01L27/088
摘要： A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth. The trench depth is preferably greater than a junction depth of the source/drain structures. In one embodiment, the formation of the trench transistor further includes, prior to the thermal oxidation of the trench floor, forming first and second ldd structures within the first and second trench ldd regions of the substrate. The first and second trench ldd structures provide conductive paths that extend from a trench channel region located beneath the trench floor to the first and the second shared source/drain structures respectively.
摘要翻译：一种半导体工艺，其中沟槽晶体管形成在一对平面晶体管之间，使得沟槽晶体管的源极/漏极区域与平面晶体管的源极/漏极区域共享。提供衬底，并且在衬底的上表面上形成第一和第二平面晶体管。沟槽晶体管的栅极电介质在衬底的上表面下方垂直位移。沟槽晶体管与第一平面晶体管共享第一共享源极/漏极结构，并且与第二平面晶体管共享第二共享源极/漏极结构。沟槽晶体管的形成优选地包括以下步骤：将沟槽蚀刻到衬底中，热氧化沟槽的底部以形成沟槽栅极电介质，并用导电材料填充沟槽以形成沟槽栅极结构。沟槽底部通过沟槽深度在衬底的上表面下方垂直移位。沟槽深度优选地大于源极/漏极结构的结深度。在一个实施例中，沟槽晶体管的形成还包括在沟槽底板的热氧化之前，在衬底的第一和第二沟槽区域内形成第一和第二层结构。第一和第二沟槽层结构提供从位于沟槽底部下方的沟槽沟道区域分别延伸到第一和第二共享源极/漏极结构的导电路径。

10. 发明授权

US5893739A Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer 失效
标题翻译：具有硼迁移势垒的非对称P沟道晶体管和选择性地形成的侧壁间隔物
公开(公告)号：US5893739A
公开(公告)日：1999-04-13
申请号：US720728
申请日：1996-10-01
申请人： Daniel Kadosh , Fred N. Hause , Jon D. Cheek
发明人： Daniel Kadosh , Fred N. Hause , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

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