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1. 发明授权

US08163626B2 Enhancing NAND flash floating gate performance 有权
标题翻译：增强NAND闪存浮栅性能
公开(公告)号：US08163626B2
公开(公告)日：2012-04-24
申请号：US12815659
申请日：2010-06-15
申请人： Johanes Swenburg , David Chu , Theresa Kramer Guarini , Yonah Cho , Udayan Ganguly , Lucien Date
发明人： Johanes Swenburg , David Chu , Theresa Kramer Guarini , Yonah Cho , Udayan Ganguly , Lucien Date
IPC分类号： H01L21/76
CPC分类号： H01L21/28273 , H01L29/66825 , H01L29/7881 , Y10S438/911
摘要： Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.
摘要翻译：本文描述的实施例通常涉及用于制造闪存设备的闪存设备和方法。在一个实施例中，提供了用于从衬底的氮化区域中选择性地除去氮的方法。该方法包括将包括邻近含氧化物层的材料层的衬底定位在处理室中，将衬底暴露于氮化工艺以将氮掺入材料层和含氧化物层的暴露区域上，并将氮化材料层和含氧化物层的氮化区域包含一定量的含氢气体和一定量的含氧气体的气体混合物，以相对于氮化材料层从含氧化物层的氮化区域选择性地除去氮气使用自由基氧化工艺。

2. 发明授权

US07303946B1 Method of manufacturing a semiconductor device using an oxidation process 失效
标题翻译：使用氧化工艺制造半导体器件的方法
公开(公告)号：US07303946B1
公开(公告)日：2007-12-04
申请号：US09559757
申请日：2000-04-27
申请人： Yoshio Ozawa , Yasumasa Suizu , Yoshitaka Tsunashima
发明人： Yoshio Ozawa , Yasumasa Suizu , Yoshitaka Tsunashima
IPC分类号： H01L21/00
CPC分类号： H01L29/7881 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02233 , H01L21/02271 , H01L21/28044 , H01L21/28202 , H01L21/28247 , H01L21/28273 , H01L21/3144 , H01L27/115 , H01L27/11521 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66825 , H01L29/7833 , Y10S438/911 , Y10S438/942 , Y10S438/947 , Y10S438/966
摘要： A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
摘要翻译：一种制造包含用作栅极绝缘膜并含有氮的氧化硅膜和用作栅电极并含有掺杂剂的多晶硅膜的MOS晶体管的方法，其布置使得栅电极形成在栅电极绝缘膜上，并且进行使用臭氧的氧化处理以充分地绕着栅电极的下边缘的形状。

3. 发明申请

US20070190798A1 REMOVING A LOW-K DIELECTRIC LAYER FROM A WAFER 审中-公开
标题翻译：从WAFER中移除一个低K介质层
公开(公告)号：US20070190798A1
公开(公告)日：2007-08-16
申请号：US11737663
申请日：2007-04-19
申请人： Hong Wang , Krishna Vepa , Paul Miller
发明人： Hong Wang , Krishna Vepa , Paul Miller
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/02079 , H01L21/31053 , Y10S438/911 , Y10S438/951
摘要： A low-k dielectric layer having a composition of silicon, oxygen and carbon, and optionally hydrogen, is removed from a test or production wafer to refresh the wafer. The low-k dielectric layer is removed by immersing a surface of the low-k dielectric layer in a first etching solution having a first composition that is believed to break the Si—O bonds in the dielectric layer; and immersing the surface of the low-k dielectric layer in a second etching solution having a second composition that is believed to break the Si—C bonds in the low-k dielectric layer.
摘要翻译：具有硅，氧和碳以及任选的氢的组成的低k电介质层从测试或生产晶片中去除以刷新晶片。通过将低k电介质层的表面浸入具有被认为破坏介电层中的Si-O键的第一组成的第一蚀刻溶液中来去除低k电介质层; 并将低k电介质层的表面浸渍在具有第二组分的第二蚀刻溶液中，该第二组分被认为会破坏低k电介质层中的Si-C键。

4. 发明申请

US20060160364A1 Refreshing wafers having low-k dielectric materials 失效
标题翻译：刷新具有低k介电材料的晶圆
公开(公告)号：US20060160364A1
公开(公告)日：2006-07-20
申请号：US11037647
申请日：2005-01-18
申请人： Hong Wang , Krishna Vepa , Paul Miller
发明人： Hong Wang , Krishna Vepa , Paul Miller
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31111 , H01L21/02079 , H01L21/31053 , Y10S438/911 , Y10S438/951
摘要： A low-k dielectric layer having a composition of silicon, oxygen and carbon is removed from a wafer. The low-k dielectric layer is removed by exposing a surface of the low-k dielectric layer to an oxygen-containing gas to oxidized the surface. The oxidized surface is immersed in an etching solution having HF and H2SO4 to etch the low-k dielectric layer. The etched surface is exposed to at least one of (i) an etching solution having H2SO4 and H2O2, and (ii) an RF or microwave energized oxygen-containing gas, to remove the low-k dielectric layer from the wafer.
摘要翻译：从晶片去除具有硅，氧和碳组成的低k电介质层。通过将低k电介质层的表面暴露于含氧气体以氧化表面来去除低k电介质层。将氧化的表面浸入具有HF和H 2 SO 4 S 4的蚀刻溶液中以蚀刻低k电介质层。蚀刻表面暴露于（i）具有H 2 SO 4 H 2和H 2 O 2 O 2的蚀刻溶液中的至少一种和（ii）RF或微波激发的含氧气体，以从晶片去除低k电介质层。

5. 发明授权

US06890832B1 Radiation hardening method for shallow trench isolation in CMOS 有权
标题翻译： CMOS中浅沟槽隔离的辐射硬化方法
公开(公告)号：US06890832B1
公开(公告)日：2005-05-10
申请号：US10292787
申请日：2002-11-12
申请人： David B. Kerwin , Bradley J Larsen
发明人： David B. Kerwin , Bradley J Larsen
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/76237 , H01L21/823481 , Y10S438/911
摘要： A radiation-hardened STI process includes implanting a partially formed wafer with a fairly large dose (1013 to 1017 ions/cm2) of a large atom group III element, such as B, Al, Ga or In at an energy between about 30 and 500 keV. The implant is followed by an implant of a large group V element, such as P, As, Sb, or Bi using similar doses and energies to the group III element. The group V element compensates the group III element. The combination of the two large atoms decreases the diffusivity of small atoms, such as B, in the implanted areas. Furthermore, the combination of the group III and group V elements in roughly equal proportions creates recombination sites and electron traps in the field oxide, resulting in a radiation hardened semiconductor device.
摘要翻译：辐射硬化的STI工艺包括以相当大的剂量（10×13×10〜17×2 / cm 2）注入部分形成的晶片大的原子组III元素，例如B，Al，Ga或In，其能量在约30和500keV之间。随后，使用与III族元素相似的剂量和能量，植入大的V族元素，例如P，As，Sb或Bi。 V族元素补偿第III族元素。两个大原子的组合降低了植入区域中小原子（如B）的扩散性。此外，III族和V族元素的组合大致相等地在场氧化物中产生复合位点和电子陷阱，导致辐射硬化的半导体器件。

6. 发明申请

US20020040764A1 Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD 失效
公开(公告)号：US20020040764A1
公开(公告)日：2002-04-11
申请号：US09920891
申请日：2001-08-02
申请人： Applied Materials, Inc.
发明人： Michael Kwan , Eric Liu
IPC分类号： H01L021/00
CPC分类号： C23C16/45523 , C23C16/045 , C23C16/4405 , C23C16/463 , C23C16/517 , C23C16/52 , H01J37/321 , H01J37/3244 , H01J2237/3327 , H01J2237/3347 , H01L21/02164 , H01L21/02274 , H01L21/30655 , H01L21/31608 , H01L21/31629 , Y10S438/911
摘要： A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. Such filling is achieved by adjusting the flow rates of the precursor gases such that the deposition to sputtering ratio during the deposition phases is within certain predetermined limits.

7. 发明授权

US06344416B1 Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions 失效
标题翻译：有意识的半导体薄膜变化来补偿径向处理差异，确定最佳的器件特性，或产生小的生产
公开(公告)号：US06344416B1
公开(公告)日：2002-02-05
申请号：US09523480
申请日：2000-03-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
IPC分类号： H01L21311
CPC分类号： H01L22/20 , C23C16/04 , C23C16/513 , C23C16/52 , H01L21/31053 , H01L21/31116 , H01L21/32137 , H01L21/76229 , H01L21/8234 , Y10S438/911
摘要： Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film. Because the semiconductor film has variations between the devices, device characteristics of the devices should be different. By measuring the device characteristics of devices having the variations, the device with the optimum device characteristic may be chosen, thereby indicating the appropriate semiconductor film thickness and/or composition. Moreover, small production runs of the same devices, having different characteristics, will allow the end user to select the appropriate devices for their needs.
摘要翻译：公开了可以在半导体制造期间引入有意的半导体膜变化以补偿径向处理差异，确定最佳器件特性或产生小的生产运行的方法和装置。本发明径向地改变半导体膜的厚度和/或组成，以补偿半导体膜中已知的半导体膜的径向变化，这是通过在半导体膜上进行随后的半导体处理步骤引起的。另外，公开了可以引入有意识的半导体薄膜变化以确定最佳的器件特性或产生小的生产运行。引入半导体薄膜变化，例如厚度变化和/或组成变化，允许制造不同的装置。可以制造多个器件，其具有半导体膜的变化。因为半导体薄膜在器件之间有变化，所以器件的器件特性应该是不同的。通过测量具有变化的器件的器件特性，可以选择具有最佳器件特性的器件，从而指示适当的半导体膜厚度和/或组成。此外，相同设备的小生产运行具有不同的特性，将允许最终用户根据需要选择适当的设备。

8. 发明授权

US06239478B1 Semiconductor structure for a MOS transistor 失效
标题翻译： MOS晶体管的半导体结构
公开(公告)号：US06239478B1
公开(公告)日：2001-05-29
申请号：US09095263
申请日：1998-06-10
申请人： Martin Kerber , Udo Schwalke
发明人： Martin Kerber , Udo Schwalke
IPC分类号： H01L2358
CPC分类号： H01L21/823462 , H01L21/28123 , Y10S438/911
摘要： The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polysilicon in the active area is raised to the same level as the adjoining field oxide areas, resulting in a planar topology.
摘要翻译： MOS晶体管具有场板和由同一多晶硅层形成的栅极的子区域。位于其下方的栅极氧化物在制造过程开始时产生，因此其显示出特别高的质量。有源区域中的多晶硅被提高到与邻接的场氧化物区域相同的水平，导致平面拓扑。

9. 发明授权

US06225167B1 Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation 有权
标题翻译：通过一次氧化步骤使用NH3氮化再生氧化产生多个氧化物厚度的方法
公开(公告)号：US06225167B1
公开(公告)日：2001-05-01
申请号：US09523988
申请日：2000-03-13
申请人： Mo-Chiun Yu , Wei-Ming Chen
发明人： Mo-Chiun Yu , Wei-Ming Chen
IPC分类号： H01L218234
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/28167 , H01L21/28202 , H01L21/28238 , H01L21/31111 , H01L21/31116 , H01L21/3144 , H01L21/31662 , H01L21/3185 , H01L21/3211 , H01L21/823462 , H01L27/112 , H01L27/11526 , H01L27/11546 , H01L29/518 , Y10S438/911
摘要： A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then the nitride layer over the high-voltage area is removed, and the substrate is wet cleaned with HF solution. The substrate surface is next oxidized to form a tunnel oxide of desired thickness over the high-voltage. In a second embodiment, a sacrificial oxide is used over the substrate for patterning the high voltage cell area and the low-voltage logic area. The sacrificial oxide is removed from the low-voltage area and the substrate is nitrided after cleaning with a solution not containing HF, thus forming a nitride layer over the low-voltage area. Then, the sacrificial oxide is removed from the high-voltage area with an HF dip, and tunnel oxide of desired thickness is formed over the same area. In this manner, oxides of multiple thicknesses are provided for the high-voltage cell area and the low-voltage peripheral logic area with one oxidation step. At the same time, with a judicious use of cleaning and nitridation, any detrimental effects of the native oxide are circumvented.
摘要翻译：公开了通过一步氧化形成不同厚度的多个氧化物的方法。在第一实施例中，提供了具有由沟槽隔离区域隔开的高压电池区域和外围低电压逻辑区域的衬底。首先氮化基底。然后去除高压区域上的氮化物层，并用HF溶液湿式清洗衬底。接着氧化氧化衬底表面以在高电压下形成所需厚度的隧道氧化物。在第二实施例中，在衬底上使用牺牲氧化物来构图高压电池区域和低电压逻辑区域。从低电压区域除去牺牲氧化物，并且在用不含HF的溶液清洗之后将衬底氮化，从而在低电压区域上形成氮化物层。然后，通过HF浸渍从高压区域去除牺牲氧化物，并且在相同的区域上形成所需厚度的隧道氧化物。以这种方式，通过一个氧化步骤为高压电池区域和低电压外围逻辑区域提供多个厚度的氧化物。同时，明智地使用清洁和氮化，可避免天然氧化物的任何有害影响。

10. 发明授权

US06211058B1 Semiconductor device with multiple contact sizes 有权
标题翻译：具有多种接触尺寸的半导体器件
公开(公告)号：US06211058B1
公开(公告)日：2001-04-03
申请号：US09353781
申请日：1999-07-15
申请人： John Jianshi Wang , Hao Fang
发明人： John Jianshi Wang , Hao Fang
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L23/5226 , H01L2924/0002 , Y10S438/911 , H01L2924/00
摘要： A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simply the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material to the etching process. Where a deep etch is required, a larger contact is used. A shallower etch through similar material uses a smaller contact to slow the etching process. As a result, the etches can complete at about the same time. The technique can be employed to etch any number of contacts. An intermediate size contact can be used where the material to be etched results in a slower etching process. A plurality of contact sizes can be used depending on the depths of etching required and the characteristics material to be etched, so that the etching for all the contacts completes at substantially the same time.
摘要翻译：具有多层的半导体器件按顺序在不同的层上使用不同尺寸的触点，以便简单地制造工艺和所需的蚀刻深度。触点尺寸是根据材料对蚀刻工艺的响应性来选择的。在需要深刻蚀时，使用较大的接触。通过类似材料的较浅蚀刻使用更小的接触来减缓蚀刻工艺。因此，蚀刻可以在大约相同的时间完成。该技术可用于蚀刻任何数量的触点。可以使用中等尺寸的接触件，其中待蚀刻的材料导致较慢的蚀刻工艺。可以根据所需的蚀刻深度和要蚀刻的特征材料使用多个接触尺寸，使得所有触点的蚀刻基本上同时完成。

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