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21. 发明授权

US07187742B1 Synchronized multi-output digital clock manager 有权
标题翻译：同步多输出数字时钟管理器
公开(公告)号：US07187742B1
公开(公告)日：2007-03-06
申请号：US09684529
申请日：2000-10-06
申请人： John D. Logue , Andrew K. Percey , F. Erich Goetting
发明人： John D. Logue , Andrew K. Percey , F. Erich Goetting
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , G06F1/10 , H03L7/0814
摘要： A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.
摘要翻译：提供数字时钟管理器。数字时钟管理器产生一个输出时钟信号，使得偏斜的时钟信号与参考时钟信号同步。此外，数字时钟管理器产生在同步期间与输出时钟信号同步的频率调整时钟信号。数字时钟管理器包括延迟锁定环和数字频率合成器。延迟锁定环产生提供给数字频率合成器的同步时钟信号。输出时钟信号通过DLL输出延迟滞后于同步时钟信号。类似地，频率调整的时钟信号通过DFS输出延迟滞后于同步时钟信号。通过将DLL输出延迟与DFS输出延迟相匹配，数字时钟管理器将输出时钟信号和频率调整后的时钟信号同步。

22. 发明授权

US06525562B1 Programmable logic device capable of preserving state data during partial or complete reconfiguration 有权
标题翻译：能够在部分或完全重新配置期间保持状态数据的可编程逻辑器件
公开(公告)号：US06525562B1
公开(公告)日：2003-02-25
申请号：US10136141
申请日：2002-04-30
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： H03K19177
CPC分类号： H03K19/17772 , H03K19/17728 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBS) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The state data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.
摘要翻译：可以重新配置可编程逻辑器件（PLD），而不会丢失从使用先前逻辑配置执行的逻辑运算导出的状态数据。根据本发明的一个PLD包括多个可配置逻辑块（CLBS）和输入/输出块（IOB）。每个CLB和IOB包括适于存储FPGA的逻辑功能的多个配置存储器单元。每个CLB和IOB还包括适于存储由PLD产生的状态数据的用户存储元件，所述状态数据由PLD执行编程的逻辑功能，诸如所选择的输入信号的组合功能。当PLD被重新配置时，PLD保留存储在用户存储单元中的数据。因此，在重新配置PLD以执行新的逻辑功能之后，状态数据可供PLD使用。

23. 发明授权

US06507211B1 Programmable logic device capable of preserving user data during partial or complete reconfiguration 有权
标题翻译：能够在部分或完全重新配置期间保留用户数据的可编程逻辑器件
公开(公告)号：US06507211B1
公开(公告)日：2003-01-14
申请号：US09363990
申请日：1999-07-29
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： G06F738
CPC分类号： H03K19/17772 , H03K19/17728 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBs) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that-results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The user data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.
摘要翻译：可以重新配置可编程逻辑器件（PLD），而不会丢失从使用先前逻辑配置执行的逻辑运算导出的状态数据。根据本发明的一个PLD包括多个可配置逻辑块（CLB）和输入/输出块（IOB）。每个CLB和IOB包括适于存储FPGA的逻辑功能的多个配置存储器单元。每个CLB和IOB还包括适于存储状态数据的用户存储元件，所述状态数据是来自执行编程逻辑功能的PLD的结果，诸如所选择的输入信号的组合功能。当PLD被重新配置时，PLD保留存储在用户存储单元中的数据。因此，在重新配置PLD以执行新的逻辑功能之后，用户数据可供PLD使用。

24. 发明授权

US06366117B1 Nonvolatile/battery-backed key in PLD 有权
标题翻译： PLD中的非易失性/电池供电密钥
公开(公告)号：US06366117B1
公开(公告)日：2002-04-02
申请号：US09724973
申请日：2000-11-28
申请人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
发明人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
IPC分类号： H04L900
CPC分类号： G06F21/76
摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.
摘要翻译：有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。根据本发明，加密设计由PLD内的密钥或密钥解密，当通过存储在非易失性存储器中的电力被去除或通过在电力被从 PLD。

25. 发明授权

US5617021A High speed post-programming net verification method 失效
标题翻译：高速后编程网验证方法
公开(公告)号：US5617021A
公开(公告)日：1997-04-01
申请号：US511574
申请日：1995-08-04
申请人： F. Erich Goetting , Wade K. Peterson , David P. Schultz
发明人： F. Erich Goetting , Wade K. Peterson , David P. Schultz
IPC分类号： G01R31/3185 , H03K19/173 , G01R31/02
CPC分类号： G01R31/318519 , H03K19/1736 , H03K19/17764 , H03K19/17796
摘要： A method and structure for verifying interconnect structure of an FPGA device after programming. In a preferred embodiment, after programming, a single wire segment on each net of a layout is pulled down to a low reference voltage. Voltage levels on all wire segments of the device are then captured and shifted out of the device for comparison to the expected values. Low voltage levels on segments expected to remain high reveal short circuit flaws. High voltage levels on segments expected to remain low reveal open circuit flaws.
摘要翻译：编程后验证FPGA器件的互连结构的方法和结构。在优选实施例中，在编程之后，布局的每个网上的单个线段被下拉到低参考电压。然后将设备的所有线段上的电压电平捕获并移出设备以与预期值进行比较。预计部分高电平的低电平显示短路缺陷。预计部分低电平的高电压电平显示开路缺陷。

26. 发明授权

US5367207A Structure and method for programming antifuses in an integrated circuit array 失效
标题翻译：用于在集成电路阵列中编程反熔丝的结构和方法
公开(公告)号：US5367207A
公开(公告)日：1994-11-22
申请号：US625732
申请日：1990-12-04
申请人： F. Erich Goetting , David B. Parlour , John E. Mahoney
发明人： F. Erich Goetting , David B. Parlour , John E. Mahoney
IPC分类号： G01R31/317 , G11C17/18 , H01L21/82 , H03K19/177 , H03K3/01 , H03K5/08 , H03K19/092
CPC分类号： G11C17/18
摘要： This invention provides a structure and method for interconnecting logic devices through line segments which can be joined by programming antifuses. One of several programming lines can be connected through an interconnect line segment to each terminal of each antifuse in the array. Interconnect line segments connected to opposite terminals of the same antifuse are connected to a different programming line in order to be able to apply different voltages to the two terminals of the antifuse. An addressing structure selectively connects interconnect line segments to their respective programming lines, and programming voltages applied to the programming lines cause a selected antifuse to be programmed. A novel addressing feature sequentially addresses two transistors for the line segments to be connected, and takes advantage of a capacitive pumped decoder to maintain the addressed transistors turned on while programming voltages are applied. The structure also allows for testing of logic devices by applying test voltages to the programming voltage lines and/or sensing logic device output on programming voltage lines. The structure and method also permit measuring resistance of the programmed antifuses. No separate testing overhead structure is needed.
摘要翻译：本发明提供了一种用于通过线段互连逻辑器件的结构和方法，其可以通过编程反熔丝来连接。几条编程线之一可以通过互连线段连接到阵列中每个反熔丝的每个端子。连接到相同反熔丝的相对端子的互连线段连接到不同的编程线，以便能够向反熔丝的两个端子施加不同的电压。寻址结构将互连线段选择性地连接到它们各自的编程线，并且施加到编程线的编程电压使得所选择的反熔丝被编程。一种新颖的寻址特征顺序地寻址要连接的线段的两个晶体管，并且利用电容性泵浦解码器来维持寻址晶体管在编程电压被施加时导通。该结构还允许通过对编程电压线上的编程电压线和/或感测逻辑器件输出施加测试电压来测试逻辑器件。该结构和方法还允许测量编程反熔丝的电阻。不需要单独的测试开销结构。

27. 发明授权

US07402443B1 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
标题翻译：使用产品选择代码为集成电路系列提供类似模具的方法部分禁用
公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
申请人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
发明人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译：提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。第三IC管芯基本上类似于第一管芯的第一部分。第二和第三包可以是相同的，并且包装的模具可以在系统中互换。当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

28. 发明授权

US07138820B2 System monitor in a programmable logic device 有权
标题翻译：可编程逻辑器件中的系统监视器
公开(公告)号：US07138820B2
公开(公告)日：2006-11-21
申请号：US10837135
申请日：2004-04-30
申请人： F. Erich Goetting , John K. Jennings , Anthony J. Collins , Patrick J. Quinn
发明人： F. Erich Goetting , John K. Jennings , Anthony J. Collins , Patrick J. Quinn
IPC分类号： H03K19/03
CPC分类号： H03K19/17732 , G01R31/3167 , G01R31/318516
摘要： Method and apparatus for a system monitor (20) embedded in a programmable logic device (10, 50, 60) are described. The system monitor (20) includes a dynamic reconfiguration port interface (205) for configuring or reconfiguring the system monitor (20) during operation thereof. The system monitor (20) includes an analog-to-digital converter (200) which is reconfigurable responsive to input via a dynamic reconfiguration port (201).
摘要翻译：描述嵌入可编程逻辑器件（10,50,60）中的系统监视器（20）的方法和装置。系统监视器（20）包括用于在其操作期间配置或重新配置系统监视器（20）的动态重新配置端口接口（205）。系统监视器（20）包括响应于经由动态重新配置端口（201）的输入而被重新配置的模数转换器（200）。

29. 发明授权

US06294930B1 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06294930B1
公开(公告)日：2001-09-25
申请号：US09479392
申请日：2000-01-06
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

30. 发明授权

US5912937A CMOS flip-flop having non-volatile storage 失效
标题翻译： CMOS触发器具有非易失性存储
公开(公告)号：US5912937A
公开(公告)日：1999-06-15
申请号：US816100
申请日：1997-03-14
申请人： F. Erich Goetting , Scott O. Frake
发明人： F. Erich Goetting , Scott O. Frake
IPC分类号： G11C14/00 , G11C16/04 , G11C19/00
CPC分类号： G11C16/0441 , G11C14/00
摘要： A flip-flop includes non-volatile storage of a bit for encryption purposes or other applications. The non-volatile bit remains in the flip-flop, substantially unaltered, irrespective of normal flip-flop operation, and is available to be recalled whenever it is needed. The flip-flop is implemented using a pair of CMOS cells. Each cell includes a floating gate formed by connecting the gates of an n-mos transistor and a p-mos transistor. One of the two floating gates is selectively charged by hot electron injection, thereby raising the threshold of that cell. Depending upon which of the two cells is programmed by this process, the flip-flop outputs a logic one or a logic zero during a recall mode.
摘要翻译：触发器包括用于加密目的或其他应用的位的非易失性存储。非易失性位保持在触发器中，基本上不改变，而不管正常的触发器操作如何，并且可以在需要时被调用。触发器使用一对CMOS单元实现。每个单元包括通过连接n-mos晶体管和p-mos晶体管的栅极形成的浮动栅极。两个浮栅中的一个通过热电子注入选择性地带电，从而提高该电池的阈值。取决于通过该过程编程的两个单元中的哪一个，触发器在调用模式期间输出逻辑1或逻辑0。

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