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1. 发明授权

US06366117B1 Nonvolatile/battery-backed key in PLD 有权
标题翻译： PLD中的非易失性/电池供电密钥
公开(公告)号：US06366117B1
公开(公告)日：2002-04-02
申请号：US09724973
申请日：2000-11-28
申请人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
发明人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
IPC分类号： H04L900
CPC分类号： G06F21/76
摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.
摘要翻译：有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。根据本发明，加密设计由PLD内的密钥或密钥解密，当通过存储在非易失性存储器中的电力被去除或通过在电力被从 PLD。

2. 发明授权

US06441641B1 Programmable logic device with partial battery backup 有权
标题翻译：具有部分电池备份的可编程逻辑器件
公开(公告)号：US06441641B1
公开(公告)日：2002-08-27
申请号：US09724735
申请日：2000-11-28
申请人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
发明人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
IPC分类号： H01L2500
CPC分类号： G06F21/76
摘要： A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.
摘要翻译：可以制造PLD以包括来自两个源的电源线，使得当PLD的电源被去除时，一部分PLD可以用电池备份。向PLD的备用部分供电的开关从外部电源和电池两者接收电力，并检测外部电源的电压，当来自外部电源的电压不足时切换到电池电力。

3. 发明授权

US06204691B1 FPGA with a plurality of input reference voltage levels grouped into sets 有权
标题翻译： FPGA具有多个输入参考电压电平分组成组
公开(公告)号：US06204691B1
公开(公告)日：2001-03-20
申请号：US09569745
申请日：2000-05-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： H03K19094
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

4. 发明授权

US06448809B2 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06448809B2
公开(公告)日：2002-09-10
申请号：US09924356
申请日：2001-08-07
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

5. 发明授权

US6049227A FPGA with a plurality of I/O voltage levels 有权
标题翻译：具有多个I / O电压电平的FPGA
公开(公告)号：US6049227A
公开(公告)日：2000-04-11
申请号：US187666
申请日：1998-11-05
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F7/38 , H03K19/003 , H03K19/094 , H03K19/177 , H03K19/0175 , H03K19/082
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

6. 发明授权

US5958026A Input/output buffer supporting multiple I/O standards 失效
标题翻译：输入/输出缓冲器支持多种I / O标准
公开(公告)号：US5958026A
公开(公告)日：1999-09-28
申请号：US837022
申请日：1997-04-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli
IPC分类号： H03K19/0175 , H03K19/0185 , G06F13/00
CPC分类号： H03K19/018585 , H03K19/017581
摘要： The invention comprises a configurable input/output buffer for an FPGA that can be configured to comply with any of two or more different I/O standards. Factors such as output drive strength, receiver type, output driver type, and output signal slew rate are configurably controlled. In some embodiments, the input power supply and the output power supply can be different from the core voltage supply. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad are configurably connected to the input reference voltage line. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage or a single output voltage supply is applied to each Input/Output Block (IOB), with IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括用于FPGA的可配置输入/输出缓冲器，其可以被配置为符合两个或更多个不同I / O标准中的任何一个。可配置控制输出驱动强度，接收器类型，输出驱动器类型，输出信号转换速率等因素。在一些实施例中，输入电源和输出电源可以不同于核心电压源。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘可配置地连接到输入参考电压线。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压或单个输出电压电源施加到每个输入/输出块（IOB），其中IOB被分组成集合。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

7. 发明授权

US06294930B1 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06294930B1
公开(公告)日：2001-09-25
申请号：US09479392
申请日：2000-01-06
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

8. 发明授权

US5877632A FPGA with a plurality of I/O voltage levels 失效
标题翻译：具有多个I / O电压电平的FPGA
公开(公告)号：US5877632A
公开(公告)日：1999-03-02
申请号：US837023
申请日：1997-04-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F7/38 , H03K19/003 , H03K19/094 , H03K19/177 , H03K19/0948
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。

9. 发明授权

US07202697B1 Programmable logic block having improved performance when functioning in shift register mode 有权
标题翻译：可编程逻辑块在移位寄存器模式下工作时具有改进的性能
公开(公告)号：US07202697B1
公开(公告)日：2007-04-10
申请号：US11152737
申请日：2005-06-14
申请人： Venu M. Kondapalli , Manoj Chirania
发明人： Venu M. Kondapalli , Manoj Chirania
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/17728
摘要： A programmable logic block reduces output delay by bypassing a final slave latch when programmed to function as a shift register. The logic block includes memory cells, a multiplexer structure, and a bypass select multiplexer (BSM). The memory cells are coupled in series to form a shift register controlled by a shift clock, each bit including two paired memory cells implementing master and slave latches. Each memory cell drives an input terminal of the multiplexer structure. The BSM drives a select terminal of the multiplexer structure and selects one signal from each pair of the memory cells. The shift clock drives one data input terminal of the BSM. When in shift register mode, the shift clock simultaneously shifts a value in each master latch to the corresponding slave latch and selects a value from one of the master latches. The output path bypasses the slave latch of the selected bit.
摘要翻译：当编程为用作移位寄存器时，可编程逻辑块通过绕过最终从锁存器来减少输出延迟。逻辑块包括存储器单元，多路复用器结构和旁路选择多路复用器（BSM）。存储器单元串联耦合以形成由移位时钟控制的移位寄存器，每个位包括实现主锁存器和从锁存器的两个配对存储器单元。每个存储单元驱动多路复用器结构的输入端。 BSM驱动多路复用器结构的选择端，并从每对存储单元中选择一个信号。移位时钟驱动BSM的一个数据输入端。在移位寄存器模式下，移位时钟同时将每个主锁存器中的值移位到相应的从锁存器，并从其中一个主锁存器中选择一个值。输出路径旁路所选位的从锁存器。

10. 发明授权

US06753722B1 Method and apparatus for voltage regulation within an integrated circuit 有权
标题翻译：集成电路内电压调节的方法和装置
公开(公告)号：US06753722B1
公开(公告)日：2004-06-22
申请号：US10354560
申请日：2003-01-30
申请人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
发明人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
IPC分类号： G05F110
CPC分类号： G05F1/56
摘要： Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.
摘要翻译：描述了用于调整集成电路内的电压的方法和装置。例如，电压调节器接收第一参考电压并产生调节电压。比较器包括用于接收第二参考电压的第一输入端和用于接收调节电压的第二输入端。比较器包括偏移电压。比较器产生指示第二参考电压和调节电压之间的差是否大于预定偏移电压的控制信号。钳位电路响应于控制信号将调节电压钳位到第二参考电压。在另一示例中，钳位电路被去除，并且多路复用器选择要耦合到电压调节器的第一参考电压或第二参考电压。通过比较第一参考电压和第二参考电压的比较器的输出来控制多路复用器。

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