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1. 发明授权

US06525562B1 Programmable logic device capable of preserving state data during partial or complete reconfiguration 有权
标题翻译：能够在部分或完全重新配置期间保持状态数据的可编程逻辑器件
公开(公告)号：US06525562B1
公开(公告)日：2003-02-25
申请号：US10136141
申请日：2002-04-30
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： H03K19177
CPC分类号： H03K19/17772 , H03K19/17728 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBS) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The state data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.
摘要翻译：可以重新配置可编程逻辑器件（PLD），而不会丢失从使用先前逻辑配置执行的逻辑运算导出的状态数据。根据本发明的一个PLD包括多个可配置逻辑块（CLBS）和输入/输出块（IOB）。每个CLB和IOB包括适于存储FPGA的逻辑功能的多个配置存储器单元。每个CLB和IOB还包括适于存储由PLD产生的状态数据的用户存储元件，所述状态数据由PLD执行编程的逻辑功能，诸如所选择的输入信号的组合功能。当PLD被重新配置时，PLD保留存储在用户存储单元中的数据。因此，在重新配置PLD以执行新的逻辑功能之后，状态数据可供PLD使用。

2. 发明授权

US06507211B1 Programmable logic device capable of preserving user data during partial or complete reconfiguration 有权
标题翻译：能够在部分或完全重新配置期间保留用户数据的可编程逻辑器件
公开(公告)号：US06507211B1
公开(公告)日：2003-01-14
申请号：US09363990
申请日：1999-07-29
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： G06F738
CPC分类号： H03K19/17772 , H03K19/17728 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBs) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that-results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The user data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.
摘要翻译：可以重新配置可编程逻辑器件（PLD），而不会丢失从使用先前逻辑配置执行的逻辑运算导出的状态数据。根据本发明的一个PLD包括多个可配置逻辑块（CLB）和输入/输出块（IOB）。每个CLB和IOB包括适于存储FPGA的逻辑功能的多个配置存储器单元。每个CLB和IOB还包括适于存储状态数据的用户存储元件，所述状态数据是来自执行编程逻辑功能的PLD的结果，诸如所选择的输入信号的组合功能。当PLD被重新配置时，PLD保留存储在用户存储单元中的数据。因此，在重新配置PLD以执行新的逻辑功能之后，用户数据可供PLD使用。

3. 发明授权

US5781756A Programmable logic device with partially configurable memory cells and a method for configuration 失效
标题翻译：具有部分可配置存储单元的可编程逻辑器件和配置方法
公开(公告)号：US5781756A
公开(公告)日：1998-07-14
申请号：US222141
申请日：1994-04-01
申请人： Lawrence C. Hung
发明人： Lawrence C. Hung
IPC分类号： G06F17/50 , H03K19/177 , G06F9/26
CPC分类号： H03K19/17756 , G06F17/5054 , H03K19/17704 , H03K19/1776
摘要： A field programmable gate array having memory cells that can be partially reconfigured comprises an array of tiles having logic blocks and routing structures, an array of associated memory cells, a data register, an address register and a memory configuration device. The data register is coupled to store data in the memory cells, and the address register is coupled to address the memory cells by column. The memory configuration device preferably comprises a register, a decoder and a control unit for receiving a bit stream including a skip command or a write command plus data. The memory configuration device allows the memory cells to be partially reconfigured by allowing each column of memory cells to be selectively written or skipped in response to the command inserted into the bit stream. The present invention also comprises a method for partially reconfiguring the memory cells including the steps of: retrieving a packet from a bit stream; determining whether the packet is a write command; if the packet is a write command, retrieving a frame of data from the bit stream and loading the frame of data into a data register; if the packet is a write command, loading the frame of data into a group of memory cells; and incrementing an address register.
摘要翻译：具有可部分重新配置的存储器单元的现场可编程门阵列包括具有逻辑块和路由结构的阵列阵列，相关联存储器单元阵列，数据寄存器，地址寄存器和存储器配置器件。数据寄存器被耦合以将数据存储在存储器单元中，并且地址寄存器被耦合以通过列对存储器单元寻址。存储器配置装置优选地包括寄存器，解码器和用于接收包括跳过命令或写入命令加数据的比特流的控制单元。存储器配置设备允许通过允许每一列存储器单元被选择性地写入或跳过来响应于插入到比特流中的命令来部分地重新配置存储器单元。本发明还包括一种用于部分重新配置存储器单元的方法，包括以下步骤：从比特流检索分组; 确定分组是否是写命令; 如果分组是写命令，则从比特流检索数据帧并将数据帧加载到数据寄存器中; 如果分组是写入命令，则将数据帧加载到一组存储器单元中; 并递增一个地址寄存器。

4. 发明授权

US5430687A Programmable logic device including a parallel input device for loading memory cells 失效
标题翻译：可编程逻辑器件包括用于加载存储器单元的并行输入器件
公开(公告)号：US5430687A
公开(公告)日：1995-07-04
申请号：US223247
申请日：1994-04-01
申请人： Lawrence C. Hung , Charles R. Erickson
发明人： Lawrence C. Hung , Charles R. Erickson
IPC分类号： H03K19/177 , G11C13/00
CPC分类号： H03K19/1776 , H03K19/17704
摘要： A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.
摘要翻译：用于配置用于可编程逻辑器件的存储器单元阵列的部分的器件包括数据寄存器，多个移位寄存器和控制单元。数据被并行加载进出数据寄存器。数据寄存器的每个输出端耦合到相应移位寄存器的串行输入端，因此数据可以同时移入移位寄存器。时钟信号由控制单元施加到移位寄存器，用于并行地串行地加载多个移位寄存器。时钟信号和负载信号优选地同时应用，直到多个移位寄存器存储要传送到存储单元的一列数据。多个移位寄存器各自具有多个数据输出。每个数据输出耦合到不同行的存储单元。然后，控制单元生成一个地址信号，将保存在多个移位寄存器中的数据列传送到存储单元。

5. 发明授权

US06429715B1 Deskewing clock signals for off-chip devices 有权
标题翻译：用于片外器件的去抖时钟信号
公开(公告)号：US06429715B1
公开(公告)日：2002-08-06
申请号：US09482741
申请日：2000-01-13
申请人： Shekhar Bapat , Lawrence C. Hung
发明人： Shekhar Bapat , Lawrence C. Hung
IPC分类号： G06F104
CPC分类号： G06F1/10 , H03L7/0814 , H03L7/087
摘要： An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree, and a plurality of interface cells on the integrated circuit function together to supply the clock signal to the plurality of external devices such that the clock signal at each of the external devices is deskewed with respect to the external clock signal. Board level design is simplified because no balanced clock tree is needed to route the clock signal from the integrated circuit to the external devices, rather each external device is coupled to a corresponding one of the interface cells via a separate external connection. Each of these external connections has an equal propagation delay. One of the interface cells supplies the clock signal back to a reference signal input of the DLL via an external connection. This external connection has the same propagation delay as the external connections to the various external devices. Matching of the propagation delays of the various external connections may be accomplished by making the external connections all of the same length.
摘要翻译：集成电路接收外部时钟信号并由此产生提供给多个外部设备的时钟信号。集成电路上的延迟锁定环（DLL），平衡时钟树和多个接口单元一起工作，以将时钟信号提供给多个外部设备，使得每个外部设备的时钟信号进行偏斜校正相对于外部时钟信号。由于不需要平衡时钟树来将集成电路的时钟信号路由到外部设备，因此板级设计被简化，而每个外部设备通过单独的外部连接耦合到相应的一个接口单元。这些外部连接中的每一个具有相等的传播延迟。其中一个接口单元通过外部连接将时钟信号提供给DLL的参考信号输入。该外部连接具有与各种外部设备的外部连接相同的传播延迟。可以通过使外部连接全部相同的长度来实现各种外部连接的传播延迟的匹配。

6. 发明授权

US06204687B1 Method and structure for configuring FPGAS 有权
标题翻译：配置FPGAS的方法和结构
公开(公告)号：US06204687B1
公开(公告)日：2001-03-20
申请号：US09374434
申请日：1999-08-13
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： G06F738
CPC分类号： G06F17/5054
摘要： An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected to the bus including a frame data register, a frame address register, a control register, a command register, and an optional data check register. The bus interface generates control signals in response to the address field and the operand field that cause one or more registers to perform predefined operations according to subsequent data words in the bit stream. For example, during configuration write operations, the bus interface enables the frame data register to receive data signals that are subsequently transferred to a configuration memory array. Conversely, during configuration read operations, the frame data register is controlled to receive data from the configuration memory array, and to transfer the data to the bus interface. Partial reconfiguration is performed by storing the address of selected frames of the configuration memory array in the frame address register, which addresses the selected frames in the configuration memory array.
摘要翻译：包括用于将来自JTAG接口或输入/输出块（IOB）接口的比特流应用到总线上的总线接口的FPGA配置电路。总线接口将头字解析成地址字段和操作数字段。几个寄存器连接到总线，包括帧数据寄存器，帧地址寄存器，控制寄存器，命令寄存器和可选的数据检查寄存器。总线接口响应于使得一个或多个寄存器根据比特流中的后续数据字执行预定义的操作的地址字段和操作数字段来生成控制信号。例如，在配置写入操作期间，总线接口使得帧数据寄存器能够接收随后传送到配置存储器阵列的数据信号。相反，在配置读取操作期间，控制帧数据寄存器以从配置存储器阵列接收数据，并将数据传送到总线接口。通过将配置存储器阵列的所选帧的地址存储在帧地址寄存器中来执行部分重新配置，该地址寄存器解决配置存储器阵列中所选择的帧。

7. 发明授权

US06191614B1 FPGA configuration circuit including bus-based CRC register 有权
标题翻译： FPGA配置电路包括基于总线的CRC寄存器
公开(公告)号：US06191614B1
公开(公告)日：2001-02-20
申请号：US09374466
申请日：1999-08-13
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： H03K19177
CPC分类号： H03M13/09
摘要： A cyclic redundancy check (CRC) register is connected to the bi-directional bus and a packet processor in a configuration circuit of an FPGA. The CRC register performs transmission error detection functions based on the command/data transmissions to various registers connected to the bus, and based on the address information transmitted from the packet processor to an address/operand decoder used to enable the various registers to receive subsequent command/data words. The CRC register calculates a check-sum value in accordance with a predetermined equation. At any time during the transmission (e.g., halfway through configuration or at the end of configuration), a pre-calculated check-sum value is transmitted to the CRC register that represents an expected check-sum value at the selected time. The pre-calculated check-sum value is then compared with the check-sum value currently stored in the CRC register. If the pre-calculated check-sum value does not equal the current check-sum value, then an error signal is generated that notifies a user that a transmission error has occurred.
摘要翻译：循环冗余校验（CRC）寄存器连接到FPGA的配置电路中的双向总线和分组处理器。 CRC寄存器基于对连接到总线的各种寄存器的命令/数据传输，并且基于从分组处理器发送到地址/操作数解码器的地址信息，执行传输错误检测功能，所述地址/操作数解码器用于使各种寄存器能够接收后续命令 /数据字。 CRC寄存器根据预定的等式计算校验和值。在传输期间的任何时间（例如，通过配置的中途或在配置结束时），预先计算的校验和值被发送到在所选择的时间表示期望的校验和值的CRC寄存器。然后将预先计算的校验和值与当前存储在CRC寄存器中的校验和值进行比较。如果预先计算的校验和值不等于当前的校验和值，则产生通知用户发生传输错误的错误信号。

8. 发明授权

US06191613B1 Programmable logic device with delay-locked loop 有权
标题翻译：具有延迟锁定环路的可编程逻辑器件
公开(公告)号：US06191613B1
公开(公告)日：2001-02-20
申请号：US09363941
申请日：1999-07-29
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： H03K19177
CPC分类号： H03K19/1774
摘要： A programmable logic device (PLD), such as a field-programmable gate array (FPGA), includes an integrated delay-locked loop that produces a lock signal internal to the FPGA. The FPGA also includes a sequencer and related global signals adapted to configure the FPGA using external configuration data. The sequencer disables the FPGA during the configuration process. The sequencer then continues to disable the fully configured FPGA until receipt of the lock signal. The configuration process, including the establishment of a valid internal clock, is controlled entirely within the FPGA. In one embodiment, an FPGA can be fully or partially reconfigured without powering down the device. The delay-locked loop maintains a lock on the clock signal so that the sequencer need not wait for the lock signal after reconfiguration.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）包括集成延迟锁定环路，其产生FPGA内部的锁定信号。 FPGA还包括一个定序器和相关的全局信号，适用于使用外部配置数据配置FPGA。定序器在配置过程中禁用FPGA。然后，定序器将继续禁用完全配置的FPGA，直到收到锁定信号。配置过程，包括建立一个有效的内部时钟，完全由FPGA控制。在一个实施例中，可以在不关闭设备的情况下完全或部分地重新配置FPGA。延迟锁定环保持对时钟信号的锁定，使得定序器在重新配置之后不需要等待锁定信号。

9. 发明授权

US06429682B1 Configuration bus interface circuit for FPGAs 有权
标题翻译： FPGA配置总线接口电路
公开(公告)号：US06429682B1
公开(公告)日：2002-08-06
申请号：US09865813
申请日：2001-05-25
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： H03K19173
CPC分类号： H03M13/09
摘要： A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.
摘要翻译：一种用于可编程逻辑器件（PLD）的总线接口电路，包括连接在两个或多个外部通信电路和配置存储器阵列之间的接口多路复用器。接口多路复用器协调所选择的一个外部通信电路和分组处理器之间的通信。分组处理器解译从所选择的外部通信电路在比特流中发送的命令/数据信息。在默认状态下，接口多路复用器将PLD的双用途输入/输出引脚连接到数据包处理器。在替代状态下，接口多路复用器将JTAG接口电路连接到分组处理器，以便于通过PLD的JTAG引脚进行配置操作。

10. 发明授权

US06262596B1 Configuration bus interface circuit for FPGAS 有权
标题翻译：用于FPGAS的配置总线接口电路
公开(公告)号：US06262596B1
公开(公告)日：2001-07-17
申请号：US09374471
申请日：1999-08-13
申请人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
发明人： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
IPC分类号： H03K19177
CPC分类号： H03M13/09
摘要： A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.
摘要翻译：一种用于可编程逻辑器件（PLD）的总线接口电路，包括连接在两个或多个外部通信电路和配置存储器阵列之间的接口多路复用器。接口多路复用器协调所选择的一个外部通信电路和分组处理器之间的通信。分组处理器解译从所选择的外部通信电路在比特流中发送的命令/数据信息。在默认状态下，接口多路复用器将PLD的双用途输入/输出引脚连接到数据包处理器。在替代状态下，接口多路复用器将JTAG接口电路连接到分组处理器，以便于通过PLD的JTAG引脚进行配置操作。

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