专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07098710B1 Multi-speed delay-locked loop 有权
标题翻译：多速延时锁定回路
公开(公告)号：US07098710B1
公开(公告)日：2006-08-29
申请号：US10719743
申请日：2003-11-21
申请人： Bernard J. New , Andrew K. Percey
发明人： Bernard J. New , Andrew K. Percey
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A delay locked loop includes a primary delay line having a plurality of series-connected delay elements, wherein each of the delay elements operates in response to a supply voltage provided on a voltage supply line. When the delay locked loop is configured to operate in response to an input clock signal having a relatively high frequency, the voltage supply line is coupled to receive a first supply voltage. When the delay locked loop is configured to operate in response to an input clock signal having a relatively low frequency, the voltage supply line is coupled to receive a second supply voltage, which is significantly lower than the first supply voltage. When operating in response to the first supply voltage, the delay elements exhibit relatively short delays. Conversely, when operating in response to the second supply voltage, the delay elements exhibit relatively long delays.
摘要翻译：延迟锁定环包括具有多个串联连接的延迟元件的主延迟线，其中每个延迟元件响应于在电压供应线上提供的电源电压而工作。当延迟锁定环被配置为响应于具有相对高频率的输入时钟信号而工作时，电压供给线被耦合以接收第一电源电压。当延迟锁定环被配置为响应于具有相对低频率的输入时钟信号而工作时，电压供给线被耦合以接收明显低于第一电源电压的第二电源电压。当响应于第一电源电压工作时，延迟元件呈现相对较短的延迟。相反，当响应于第二电源电压进行操作时，延迟元件表现出较长的延迟。

2. 发明授权

US06775342B1 Digital phase shifter 有权
标题翻译：数字移相器
公开(公告)号：US06775342B1
公开(公告)日：2004-08-10
申请号：US09684540
申请日：2000-10-06
申请人： Steven P. Young , John D. Logue , Andrew K. Percey , F. Erich Goetting , Alvin Y. Ching
发明人： Steven P. Young , John D. Logue , Andrew K. Percey , F. Erich Goetting , Alvin Y. Ching
IPC分类号： H04L2500
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal. In a second fixed mode, the digital phase shifter introduces delay to the reference clock signal. In a first variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the reference clock signal. In a second variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the skew clock signal.
摘要翻译：在延迟锁定环路使参考时钟信号与偏斜时钟信号同步之后，数字移相器可用于相对于参考时钟信号将偏斜的时钟信号移位一小段量。在延迟锁定环路的主路径上的延迟线的抽头/微调设置可被发送到数字移相器，由此通知数字移相器参考时钟信号的周期。作为响应，数字移相器提供相位控制信号，其将参考时钟信号的周期的延迟引入参考时钟信号或偏斜时钟信号。相位控制信号与参考时钟信号的周期的预定分数成比例。数字移相器可以控制在多种模式下工作。在第一固定模式中，数字移相器将延迟引入到偏斜时钟信号。在第二固定模式中，数字移相器将延迟引入参考时钟信号。在第一可变模式中，数字移相器可以通过控制参考时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。在第二可变模式中，数字移相器可以通过控制偏斜时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。

3. 发明授权

US07187742B1 Synchronized multi-output digital clock manager 有权
标题翻译：同步多输出数字时钟管理器
公开(公告)号：US07187742B1
公开(公告)日：2007-03-06
申请号：US09684529
申请日：2000-10-06
申请人： John D. Logue , Andrew K. Percey , F. Erich Goetting
发明人： John D. Logue , Andrew K. Percey , F. Erich Goetting
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , G06F1/10 , H03L7/0814
摘要： A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.
摘要翻译：提供数字时钟管理器。数字时钟管理器产生一个输出时钟信号，使得偏斜的时钟信号与参考时钟信号同步。此外，数字时钟管理器产生在同步期间与输出时钟信号同步的频率调整时钟信号。数字时钟管理器包括延迟锁定环和数字频率合成器。延迟锁定环产生提供给数字频率合成器的同步时钟信号。输出时钟信号通过DLL输出延迟滞后于同步时钟信号。类似地，频率调整的时钟信号通过DFS输出延迟滞后于同步时钟信号。通过将DLL输出延迟与DFS输出延迟相匹配，数字时钟管理器将输出时钟信号和频率调整后的时钟信号同步。

4. 发明授权

US07046052B1 Phase matched clock divider 有权
标题翻译：相位匹配时钟分频器
公开(公告)号：US07046052B1
公开(公告)日：2006-05-16
申请号：US10837210
申请日：2004-04-30
申请人： Andrew K. Percey , Raymond C. Pang
发明人： Andrew K. Percey , Raymond C. Pang
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/50
摘要： A phase matched clock divider includes a first feed-through flip-flop that receives a first input clock signal, and in response, provides a first output clock signal having the same frequency. The first feed-through flip-flop is enabled and disabled in response to a first reset signal. A plurality of series-connected flip-flops each receives the first input clock signal, and in response, provides a divided output clock signal. Each of the series-connected flip-flops is enabled and disabled in response to a second reset signal. The first and second release signals asynchronously disable the associated flip-flops in response to a third reset signal. The first release signal synchronously enables the first feed-through flip-flop in response to the third reset signal and a release clock signal. The second release signal enables the series-connected flip-flops in response to the third reset signal and a release control signal.
摘要翻译：相位匹配时钟分频器包括接收第一输入时钟信号的第一馈通触发器，并且作为响应，提供具有相同频率的第一输出时钟信号。响应于第一复位信号，第一馈通触发器被使能和禁止。多个串联触发器各自接收第一输入时钟信号，作为响应，提供分频的输出时钟信号。每个串联的触发器响应于第二复位信号被使能和禁止。响应于第三复位信号，第一和第二释放信号异步地禁用相关联的触发器。响应于第三复位信号和释放时钟信号，第一释放信号同步使第一馈通触发器使能。第二释放信号使得串联连接的触发器响应于第三复位信号和释放控制信号。

5. 发明授权

US07010014B1 Digital spread spectrum circuitry 有权
标题翻译：数字扩频电路
公开(公告)号：US07010014B1
公开(公告)日：2006-03-07
申请号：US09684528
申请日：2000-10-06
申请人： Andrew K. Percey , John D. Logue , F. Erich Goetting , Paul G. Hyland
发明人： Andrew K. Percey , John D. Logue , F. Erich Goetting , Paul G. Hyland
IPC分类号： H04B1/69 , H03D3/24 , H03L7/00 , H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly different frequencies in successive periods. For example, the frequency of a 100 MHz clock signal can be adjusted to have frequencies of approximately 98, 98.5, 99, 99.5, 100, 100.5, 101, 101.5, and 102 MHz during different periods. Because the frequencies are spread in 0.5 MHz increments, only three frequencies are included in any 1 MHz window. As a result, ⅔ of the energy of the clock signal is not included when determining whether the clock signal meets the FCC electromagnetic emission requirements. By spreading the frequencies above and below the base frequency in a regular manner, the average frequency of the clock signal becomes equal to the base frequency.
摘要翻译：偏移时钟信号的频率在基频周围抖动，从而使该时钟信号能够符合FCC在指定窗口内对电磁辐射的要求。引入延迟使得时钟信号在连续的周期中表现出稍微不同的频率。例如，100MHz时钟信号的频率可以在不同时段期间被调整为具有约98,98.5,99,99.5,100,150.5,101,101.5和102MHz的频率。由于频率以0.5 MHz为单位进行扩展，所以在1 MHz窗口中只能包含三个频率。因此，当确定时钟信号是否满足FCC电磁辐射要求时，不包括时钟信号的能量的2/3。通过以规则的方式扩展基频以上的频率，时钟信号的平均频率等于基频。

6. 发明授权

US06983394B1 Method and apparatus for clock signal performance measurement 有权
标题翻译：时钟信号性能测量的方法和装置
公开(公告)号：US06983394B1
公开(公告)日：2006-01-03
申请号：US10351033
申请日：2003-01-24
申请人： Shawn K. Morrison , Andrew K. Percey , John D. Logue , James M. Simkins , Nicholas J. Sawyer
发明人： Shawn K. Morrison , Andrew K. Percey , John D. Logue , James M. Simkins , Nicholas J. Sawyer
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G01R31/31708 , G01R31/31725 , H04L7/0337
摘要： Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.
摘要翻译：描述了用于提供时钟信号的抖动和偏斜的量度的方法和装置。时钟信号可以用作数字电路的输入。在一个实施例中，数字延迟电路与处理电路结合使用，以连续测量输入时钟信号的抖动，从而随时间提供时钟信号性能测量。在另一个实施例中，使用一对数字延迟电路来连续测量参考时钟信号和输入时钟信号之间的偏差或延迟，从而提供输入时钟信号随时间偏移的测量。数字延迟电路形成在片上，因此可以提供抖动或偏斜的片上确定。

7. 发明授权

US06400735B1 Glitchless delay line using gray code multiplexer 失效
标题翻译：使用灰度复用器的无毛刺延迟线
公开(公告)号：US06400735B1
公开(公告)日：2002-06-04
申请号：US09102704
申请日：1998-06-22
申请人： Andrew K. Percey
发明人： Andrew K. Percey
IPC分类号： H04J306
CPC分类号： H03L7/0814 , H03K5/133
摘要： A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.
摘要翻译：提供了使用格雷码多路复用器的无毛刺延迟线。无毛刺延迟线将多抽头延迟电路与格雷码多路复用器相结合。具体地，多抽头延迟电路在多个顺序排列的输出端上提供多个顺序排列的延迟输出信号。格雷码复用器具有耦合到顺序排列的延迟输出端的多个输入端。格雷码多路复用器通过将格雷码值驱动到格雷码多路复用器的控制端上来选择多抽头延迟电路的特定延迟输出端。延迟线提供的延迟通过增加格雷码多路复用器的控制端上的格雷码值而增加，并通过减少控制终端上的格雷码值而减小。当将格雷码值递增或递减1时，消除控制线上的竞争条件。

8. 发明授权

US06204689B1 Input/output interconnect circuit for FPGAs 有权
标题翻译： FPGA的输入/输出互连电路
公开(公告)号：US06204689B1
公开(公告)日：2001-03-20
申请号：US09321513
申请日：1999-05-27
申请人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
发明人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
IPC分类号： H01L2500
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles. In another embodiment, various ends of bi-directional intermediate-length buses are terminated to long lines through programmable interconnection points (PIPs). In another embodiment, PIPs are provided to enable horizontal long lines to be connected to horizontal intermediate-length buses, which in turn, can be connected to vertical long lines, thereby providing a low-skew, high fanout routing network.
摘要翻译：提供输入/输出互连（IOI）电路用于将输入/输出（IO）块耦合到现场可编程门阵列（FPGA）中的可配置逻辑块阵列。每个瓦片包括可配置逻辑块和包括多个中长度总线的可编程互连结构。中间长度总线是交错的，使得只有由逻辑块路由的中间长度总线的子集连接到逻辑块。 IOI电路包括用于终止中长度总线的阵列周边的路由电路。在一个实施例中，路由电路将单向中长度总线的各端连接在U形结构中，从而利用所有的中长度总线，并在瓦片中保持中长度总线的规则图案。在另一个实施例中，双向中间长度总线的各个端点通过可编程互连点（PIP）终止于长行。在另一个实施例中，提供PIP以使得水平长线能够连接到水平中间长度总线，其又可以连接到垂直长线，从而提供低偏移，高扇出路由网络。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式