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1. 发明公开

KR20100031896A Apparatus and method for forming semiconductor devices 有权
标题翻译：用于形成半导体器件的装置和方法
公开(公告)号：KR20100031896A
公开(公告)日：2010-03-25
申请号：KR20080090756
申请日：2008-09-16
申请人： SAMSUNG ELECTRONICS CO LTD , KOOKJE KOKUSAI ELECTRIC KOREA
发明人： PARK YOUNG SOO , AHN JUNG IL , KIM MYEONG JIN , CHA SANG YEOB , HWANG WAN GOO , AN YOUNG SAM
IPC分类号： H01L21/20 , H01L21/22
CPC分类号： H01L21/67109 , C30B35/00
摘要： PURPOSE: An apparatus and a method for manufacturing a semiconductor device are provided to improve deposition uniformity between wafers by forming a thin film by vertically stacking a plurality of wafers. CONSTITUTION: An apparatus(1) for manufacturing a semiconductor device includes an inner tube(120), an outer tube(140), a gas supply unit(240), a gas exhaust unit(280), and a plate(400). The outer tube surrounds the inner tube. The gas supply unit supplies the gas. The gas flows from the lower side to the upper side of the inner tube. The gas exhaust unit exhausts the gas. A plate includes at least one through-hole. The gas flows through the through-hole.
摘要翻译：目的：提供一种用于制造半导体器件的装置和方法，以通过垂直堆叠多个晶片形成薄膜来提高晶片之间的沉积均匀性。构成：用于制造半导体器件的装置（1）包括内管（120），外管（140），气体供应单元（240），排气单元（280）和板（400）。外管围绕内管。气体供应单元供应气体。气体从内管的下侧向上侧流动。排气单元排气。板包括至少一个通孔。气体流过通孔。

2. 发明授权

KR100741856B1 METHOD OF FORMING SOI SUBSTRATE AND THE SUBSTRATE SO FORMED 无效
标题翻译：形成SOI衬底的方法和形成的衬底
公开(公告)号：KR100741856B1
公开(公告)日：2007-07-16
申请号：KR20060036698
申请日：2006-04-24
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK YOUNG SOO , CHO KYOO CHUL , CHOI SOO YEOL , KANG TAE SOO , LEE YOON HEE
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L29/66772 , H01L29/7841 , H01L29/785 , H01L29/7851 , H01L29/78639 , H01L29/7881
摘要： A method for forming an SOI(silicon on insulator) substrate is provided to securely prevent a leakage current by forming a thermal oxide layer on a semiconductor substrate so that an oxygen density is uniform in an oxide layer. A thermal oxide layer is formed on a semiconductor substrate(1). While the thermal oxide layer is patterned to form a thermal oxide layer pattern(3a), a part of the semiconductor substrate is exposed. A first semiconductor single crystalline layer(4d) is formed, covering the sidewall and the upper surface of the thermal oxide layer pattern and coming in contact with the exposed semiconductor substrate. A second semiconductor single crystalline layer(4e) is formed on the first semiconductor single crystalline layer. A heat treatment is performed on the first semiconductor single crystalline layer. A etch process for planarization is performed to eliminate a part of the upper part of the first semiconductor single crystalline layer.
摘要翻译：提供了一种用于形成SOI（绝缘体上硅）衬底的方法，以通过在半导体衬底上形成热氧化层以使氧密度在氧化物层中均匀而可靠地防止漏电流。在半导体基板（1）上形成热氧化层。当热氧化物层被图案化以形成热氧化物层图案（3a）时，半导体衬底的一部分被暴露。形成第一半导体单晶层（4d），覆盖热氧化物层图案的侧壁和上表面并与暴露的半导体衬底接触。在第一半导体单晶层上形成第二半导体单晶层（4e）。对第一半导体单晶层进行热处理。执行用于平坦化的蚀刻工艺以消除第一半导体单晶层的上部的一部分。

3. 发明公开

KR20120032329A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：KR20120032329A
公开(公告)日：2012-04-05
申请号：KR20100093923
申请日：2010-09-28
申请人： SAMSUNG ELECTRONICS CO LTD , SAMSUNG LED CO LTD
发明人： TAK YOUNG JO , LEE JAE WON , PARK YOUNG SOO , KIM JUN YOUN
IPC分类号： H01L33/12
CPC分类号： H01L21/0254 , H01L21/02378 , H01L21/02381 , H01L21/02458 , H01L21/02502 , H01L21/02505 , H01L21/02507 , H01L21/0259 , H01L21/02642 , H01L21/02664 , H01L33/007 , H01L33/12 , H01L33/32
摘要： PURPOSE: A semiconductor device is provided to increase stress compensation effects due to an intermediate layer by effectively reducing penetration potential through a masking layer, thereby reducing tensile stress and defect density. CONSTITUTION: A first nitride semiconductor layer(12) is arranged on a substrate. A masking layer(13) is arranged on the first nitride semiconductor layer. A second nitride semiconductor layer(14) is arranged on the masking layer. An intermediate layer(15) is arranged on the second nitride semiconductor layer. A third nitride semiconductor layer(16) is arranged on the intermediate layer.
摘要翻译：目的：提供一种半导体器件，通过有效地减少通过掩模层的穿透电位来增加由于中间层引起的应力补偿效应，从而降低拉伸应力和缺陷密度。构成：第一氮化物半导体层（12）被布置在衬底上。掩模层（13）设置在第一氮化物半导体层上。第二氮化物半导体层（14）布置在掩模层上。中间层（15）布置在第二氮化物半导体层上。第三氮化物半导体层（16）布置在中间层上。

4. 发明公开

KR20120023436A Method of vertically growing galium nitride 审中-公开
标题翻译：垂直生长氮化铵的方法
公开(公告)号：KR20120023436A
公开(公告)日：2012-03-13
申请号：KR20100086594
申请日：2010-09-03
申请人： SAMSUNG ELECTRONICS CO LTD , UNIV YONSEI IACF
发明人： YANG MOON SEUNG , PARK YOUNG SOO , KIM TAEK , KIM JUN YOUN , CHOI HEON JIN , HA RYOUNG
IPC分类号： B82B3/00 , H01L21/20
CPC分类号： H01L21/02603 , B82Y40/00 , H01L21/20
摘要： PURPOSE: A vertical grow method of gallium nitride nanowire is provided to grow gallium nitride nanowire vertically on a substrate by using two or more catalytic substances. CONSTITUTION: A vertical grow method of gallium nitride nanowire comprises the following steps: successively evaporating a first catalyst layer(120) and a second catalyst layer(130) on a substrate(110); heating the substrate at a first temperature; supplying a gallium precursor and a nitrogen precursor to the substrate; and vertically growing the gallium nitride nanowire on top of the substrate. The first and the second catalyst layers are respectively formed in 0.1-10nm thickness. The first catalyst layer is composed of noble metal and the second catalyst layer is composed of transition metal. The first catalyst layer is formed with one of the following metals: Au, Pt, and Pd. The second catalyst layer is formed with one of the following metals: Ni, Al, and Fe. The second catalyst layer has higher melting temperature than the first catalyst layer.
摘要翻译：目的：提供氮化镓纳米线的垂直生长方法，通过使用两种或更多种催化物质在衬底上垂直生长氮化镓纳米线。构成：氮化镓纳米线的垂直生长方法包括以下步骤：在衬底（110）上连续蒸发第一催化剂层（120）和第二催化剂层（130）; 在第一温度下加热衬底; 向所述衬底供应镓前体和氮前体; 并在衬底的顶部垂直生长氮化镓纳米线。第一催化剂层和第二催化剂层分别形成为0.1-10nm厚度。第一催化剂层由贵金属构成，第二催化剂层由过渡金属组成。第一催化剂层由以下金属之一形成：Au，Pt和Pd。第二催化剂层由以下金属之一形成：Ni，Al和Fe。第二催化剂层的熔融温度比第一催化剂层高。

5. 发明公开

KR20070119944A METHOD OF FORMING SILICON NANO CRYSTALS AND METHOD OF MANUFACTURING MEMORY DEVICE USING THE SAME 审中-公开
标题翻译：形成硅纳米晶体的方法和使用其制造存储器件的方法
公开(公告)号：KR20070119944A
公开(公告)日：2007-12-21
申请号：KR20060054531
申请日：2006-06-16
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHA YOUNG KWAN , PARK YOUNG SOO , PARK SANG JIN , SHIN SANG MIN , LIM HYUCK , SHIN JUNG HOON
IPC分类号： H01L21/20 , H01L21/8247
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/02532 , H01L21/02595 , H01L21/02601 , H01L21/02667 , H01L29/42332
摘要： A method for forming silicon nano crystals is provided to prevent an oxide layer(tunneling layer) from being damaged by diffused silicon and obtain nano crystals with uniform size and distribution by performing an annealing process on an amorphous silicon layer in an incomplete oxidation condition. An amorphous layer(24) is formed on a base layer. An incomplete oxidation process is performed on the amorphous layer so that the amorphous layer is transformed into an oxide layer(22) including nano crystals. In the incomplete oxidation of the amorphous layer, an annealing process can be performed on the amorphous layer at a temperature of 900 °C and for a time interval of 2-3 minutes in a gas atmosphere of nitrogen of 90 percent and oxygen of 10 percent.
摘要翻译：提供一种形成硅纳米晶体的方法，以防止扩散硅损坏氧化物层（隧道层），并通过在不完全氧化条件下对非晶硅层进行退火处理获得具有均匀尺寸和分布的纳米晶体。在基底层上形成非晶层（24）。对非晶层进行不完全氧化处理，使得非晶层转变成包括纳米晶体的氧化物层（22）。在非晶层的不完全氧化中，可以在90℃的氮气气氛中在900℃的温度下对非晶层进行退火处理，时间间隔为2-3分钟，氧气为10％。

6. 发明公开

KR20070111616A NONVOLATILE MEMORY DEVICE COMPRISING SI NANOCRYSTAL AS FLOATING GATE AND METHOD OF MANUFACTURING THE SAME 无效
标题翻译：包含作为浮动闸门的纳米晶体的非易失性存储器件及其制造方法
公开(公告)号：KR20070111616A
公开(公告)日：2007-11-22
申请号：KR20060044639
申请日：2006-05-18
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHA YOUNG KWAN , CHOI SUK HO , HAN KYU IL , PARK YOUNG SOO , PARK SANG JIN , PARK YONG MIN
IPC分类号： H01L27/115
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： An NVM(non-volatile memory) device including a silicon nano crystal as a floating gate is provided to improve a retention time characteristic of an NFGM(nano-floating gate memory) device by making the NFGM device include a tunneling layer, a nano crystal layer and a control oxide layer and by installing an intermediate insulation layer of a predetermined thickness, if the nano crystal layer is a double layer, into the double layer. A memory device including a gate stack(S) is formed on a substrate(40) between a source and a drain. The gate stack includes a tunneling layer(42), a storage node and a control oxide layer(46) wherein the control oxide layer has a thickness of 5~30 nm. The storage node can include a first nano crystal layer, an intermediate insulation layer and a second nano crystal layer. The intermediate insulation layer can be made of a silicon oxide layer having a thickness of 3~5 nm or so.
摘要翻译：提供了包括作为浮动栅极的硅纳米晶体的NVM（非易失性存储器）器件，以通过使NFGM器件包括隧道层，纳米晶体，以提高NFGM（纳米浮动栅极存储器）器件的保留时间特性层和控制氧化物层，并且如果纳米晶层是双层，则通过将预定厚度的中间绝缘层安装到双层中。包括栅极堆叠（S）的存储器件形成在源极和漏极之间的衬底（40）上。栅极堆叠包括隧道层（42），存储节点和控制氧化物层（46），其中控制氧化物层具有5〜30nm的厚度。存储节点可以包括第一纳米晶体层，中间绝缘层和第二纳米晶体层。中间绝缘层可以由厚度为3〜5nm左右的氧化硅层制成。

7. 发明授权

KR100763912B1 A-SI TFT AND ORGANIC LIGHT EMITTING DISPLAY EMPLOYING THE SAME 无效
标题翻译： A-SI TFT和有机发光显示器使用它
公开(公告)号：KR100763912B1
公开(公告)日：2007-10-05
申请号：KR20060034673
申请日：2006-04-17
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK JAE CHUL , PARK YOUNG SOO , CHA YOUNG KWAN
IPC分类号： H01L29/786 , H01L51/52
CPC分类号： H01L29/78606 , H01L27/1296 , H01L27/3244 , H01L29/78603 , H01L29/78663
摘要： An amorphous silicon TFT and an organic light emissive display with the same are provided to recover stably a threshold voltage by applying the heat using a heat generating portion. An amorphous silicon TFT(10) includes an amorphous silicon TFT portion and a heat generating portion. The amorphous silicon TFT portion includes a gate electrode(14), a gate insulating layer(15), an amorphous silicon layer(17) and source/drain electrodes(18,19). The amorphous silicon TFT portion is formed on a substrate(11). The heat generating portion(12) is used for recovering a threshold voltage by transmitting the heat to the amorphous silicon layer. An insulating layer is interposed between the substrate and the amorphous silicon TFT portion. The heat generating portion is located at a predetermined portion corresponding to the amorphous silicon layer between the substrate and the insulating layer.
摘要翻译：提供非晶硅TFT和具有该非晶硅TFT的有机发光显示器，以通过使用发热部分施加热量来稳定地恢复阈值电压。非晶硅TFT（10）包括非晶硅TFT部分和发热部分。非晶硅TFT部分包括栅极（14），栅极绝缘层（15），非晶硅层（17）和源极/漏极（18,19）。非晶硅TFT部分形成在基板（11）上。发热部（12）用于通过将热传递到非晶硅层来恢复阈值电压。在基板和非晶硅TFT部分之间设置有绝缘层。发热部分位于与衬底和绝缘层之间的非晶硅层对应的预定部分。

8. 发明公开

KR20100030401A 트랜지스터, 이를 포함하는 인버터 및 이들의 제조방법 有权
标题翻译：晶体管，包含其的逆变器和制造晶体管和逆变器的方法
公开(公告)号：KR20100030401A
公开(公告)日：2010-03-18
申请号：KR20080089337
申请日：2008-09-10
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HUAXIANG YIN , SONG I HUN , KIM SUN IL , PARK YOUNG SOO
IPC分类号： H01L21/786
CPC分类号： H01L29/7869 , H01L21/84 , H01L27/11573 , H01L27/1203 , H01L27/1225 , H01L27/1237 , H01L29/66833 , H01L29/792
摘要： 트랜지스터, 상기트랜지스터를포함하는인버터및 이들의제조방법에관해개시되어있다. 개시된트랜지스터는게이트절연층에전하트랩영역을갖는다. 상기전하트랩영역에전하를트랩시킴으로써문턱전압을양(+)의방향으로이동시킬수 있다. 이러한트랜지스터는증가형(enhancement mode)의산화물박막트랜지스터일수 있고, 인버터의구성요소로사용될수 있다.
摘要翻译：目的：提供一种晶体管，包括该晶体管的逆变器和用于制造晶体管和逆变器的方法，以获得使用其阈值电压增加的氧化物薄膜晶体管具有优异的操作性能的增强/耗尽型逆变器。构成：栅极（G1，G2）和沟道层（C1，C2）间隔开。栅极绝缘层（GI1，GI2）布置在栅电极和沟道层之间，并且包括电荷捕获区域。源电极（S1，S2）和漏电极（D1，D2）连接到沟道层的两侧。电荷被俘获在电荷捕获区域中。阈值电压被传送到正方向。

9. 发明公开

KR20080072348A METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE FABRICATED THEREBY 无效
标题翻译：用于制造半导体存储器件的方法和其制造的半导体存储器件
公开(公告)号：KR20080072348A
公开(公告)日：2008-08-06
申请号：KR20070010990
申请日：2007-02-02
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK YOUNG SOO , CHOI SAM JONG , CHO KYOO CHUL , KANG TAE SOO
IPC分类号： H01L27/115
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/26506 , H01L29/42332 , H01L29/7881 , H01L29/66825
摘要： A semiconductor memory device and a manufacturing method thereof are provided to compensate for a decrease in a width of dielectric layer by forming nano crystals in respective dielectric layers. A multilayer dielectric layer structure having first and second dielectric layers(110,120) is formed on a semiconductor substrate(100). The first dielectric layer includes an ion implantation layer. The second dielectric layer does not include the ion implantation layer. The dielectric layer structure is heated-treated, such that ions are diffused from the ion implantation layer to the second dielectric layer. Nano crystals(114,124) are formed in the respective first and second dielectric layers. A gate electrode is formed on the dielectric layer structure.
摘要翻译：提供半导体存储器件及其制造方法，以通过在各介电层中形成纳米晶体来补偿介电层的宽度的减小。具有第一和第二电介质层（110,120）的多层电介质层结构形成在半导体衬底（100）上。第一电介质层包括离子注入层。第二电介质层不包括离子注入层。电介质层结构被加热处理，使得离子从离子注入层扩散到第二介电层。在相应的第一和第二介电层中形成纳米晶体（114,124）。在电介质层结构上形成栅电极。

10. 发明授权

KR100604938B1 REFLECTION MASK FOR EUVL LITHOGRAPHY, FABRICATING METHOD OF THE SAME 有权
标题翻译：反射掩模用于EUVL光刻，其制作方法
公开(公告)号：KR100604938B1
公开(公告)日：2006-07-19
申请号：KR20050045218
申请日：2005-05-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM SUK PIL , SONG I HUN , PARK YOUNG SOO , CHANG SEUNG HYUK , KIM HOON
IPC分类号： H01L21/027 , G03F1/22 , G03F1/24
CPC分类号： G21K1/062 , B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/26
摘要： 극자외선용 반사마스크 및 그 제조 방법이 개시된다.
개시되는 반사마스크는 기판, 상기 기판 상에 형성되고, 극자외선을 반사시킬 수 있는 재료로 이루어진 하부 다중 반사층, 상기 하부 다중 반사층 상에 형성되고 극자외선을 반사시킬 수 있는 상부 다중 반사층, 및 상기 상하부 반사층 사이에 형성되고, 상부 반사층에서 반사한 것과 하부 반사층에서 반사한 것이 서로 소멸간섭을 이루도록 하는 소정 패턴 형상의 위상반전층을 포함한다.
본 발명에 따른 반사마스크 및 그 제조방법에 의하면, 섀도우 효과의 감소와 불필요한 극자외선을 제거하여 포토리소그라피 공정에 있어서 마스크 상에 설계된 패턴 형상이 실리콘 웨이퍼에 정확하게 구현될 수 있도록 하는 장점이 있으며, 상기 위상반전층의 재질이 상기 반사층과 흡수층의 재질과 동일하게 할 수 있어 그 제조 공정이 수월해지는 장점이 있다.

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