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1. 发明授权

KR100741856B1 METHOD OF FORMING SOI SUBSTRATE AND THE SUBSTRATE SO FORMED 无效
标题翻译：形成SOI衬底的方法和形成的衬底
公开(公告)号：KR100741856B1
公开(公告)日：2007-07-16
申请号：KR20060036698
申请日：2006-04-24
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK YOUNG SOO , CHO KYOO CHUL , CHOI SOO YEOL , KANG TAE SOO , LEE YOON HEE
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L29/66772 , H01L29/7841 , H01L29/785 , H01L29/7851 , H01L29/78639 , H01L29/7881
摘要： A method for forming an SOI(silicon on insulator) substrate is provided to securely prevent a leakage current by forming a thermal oxide layer on a semiconductor substrate so that an oxygen density is uniform in an oxide layer. A thermal oxide layer is formed on a semiconductor substrate(1). While the thermal oxide layer is patterned to form a thermal oxide layer pattern(3a), a part of the semiconductor substrate is exposed. A first semiconductor single crystalline layer(4d) is formed, covering the sidewall and the upper surface of the thermal oxide layer pattern and coming in contact with the exposed semiconductor substrate. A second semiconductor single crystalline layer(4e) is formed on the first semiconductor single crystalline layer. A heat treatment is performed on the first semiconductor single crystalline layer. A etch process for planarization is performed to eliminate a part of the upper part of the first semiconductor single crystalline layer.
摘要翻译：提供了一种用于形成SOI（绝缘体上硅）衬底的方法，以通过在半导体衬底上形成热氧化层以使氧密度在氧化物层中均匀而可靠地防止漏电流。在半导体基板（1）上形成热氧化层。当热氧化物层被图案化以形成热氧化物层图案（3a）时，半导体衬底的一部分被暴露。形成第一半导体单晶层（4d），覆盖热氧化物层图案的侧壁和上表面并与暴露的半导体衬底接触。在第一半导体单晶层上形成第二半导体单晶层（4e）。对第一半导体单晶层进行热处理。执行用于平坦化的蚀刻工艺以消除第一半导体单晶层的上部的一部分。

2. 发明授权

KR100735534B1 NANO CRYSTAL NONVOLATILE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION METHOD THEREOF 无效
标题翻译：纳米晶体非线性半导体集成电路器件及其制造方法
公开(公告)号：KR100735534B1
公开(公告)日：2007-06-28
申请号：KR20060030581
申请日：2006-04-04
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHOI SAM JONG , CHO KYOO CHUL , CHOI SOO YEOL , KIM YONG KWON , PARK YOUNG SOO , IHN CHAN KOOK , PARK HAE JIN , KIM SANG SIG
IPC分类号： H01L27/115
CPC分类号： H01L21/265 , B82Y10/00 , G11C2216/06 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L29/1037 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66825 , H01L29/7881 , H01L29/7885 , H01L29/7887
摘要： A nano crystal nonvolatile semiconductor integrated device and a manufacturing method thereof are provided to dramatically reduce leakage of trapped charges by using a nano crystal as a charge trap site. An insulating layer(110b) is formed on a substrate(100). The insulating layer has an energy band gap in excess of 5 eV and a dielectric constant in excess of 7. Ions for forming a nano crystal(130_NC) are injected in the insulating layer with ion implantation energy of 7 to 10 KeV. An annealing process is performed to form a charge trap layer(150a) where a plurality of charge trap nano crystal are embedded. An annealing process is performed before the ion injection for forming the nano crystal.
摘要翻译：提供了一种纳米晶体非易失性半导体集成器件及其制造方法，以通过使用纳米晶体作为电荷陷阱位点来显着减少捕获电荷的泄漏。绝缘层（110b）形成在基板（100）上。绝缘层具有超过5eV的能带隙和超过7的介电常数。用于形成纳米晶体的离子（130_NC）以7至10KeV的离子注入能量注入绝缘层中。进行退火处理以形成其中嵌入多个电荷陷阱纳米晶体的电荷陷阱层（150a）。在用于形成纳米晶体的离子注入之前进行退火处理。

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