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2. 发明专利

JP4217247B2 Variable transconductance circuit 有权
公开(公告)号：JP4217247B2
公开(公告)日：2009-01-28
申请号：JP2006110550
申请日：2006-04-13
申请人：パナソニック株式会社
发明人：浩安森川 , 真三康片田 , 麻里絵西中
IPC分类号： H03G3/10 , H03F3/45 , H03F3/68
CPC分类号： H03F3/45197 , H03F3/45201 , H03F2203/45288 , H03F2203/45356 , H03F2203/45471 , H03F2203/45652 , H03F2203/45668 , H03G1/0029 , H03G7/001

3. 发明专利

JP2008092266A Differential circuit 审中-公开
标题翻译：差分电路
公开(公告)号：JP2008092266A
公开(公告)日：2008-04-17
申请号：JP2006270690
申请日：2006-10-02
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： KIMURA KATSUHARU
IPC分类号： H03F3/45 , H03F1/32
CPC分类号： H03F3/45197 , H03F1/3211 , H03F3/45183 , H03F3/45188 , H03F3/45632 , H03F2203/45024 , H03F2203/45062 , H03F2203/45318 , H03F2203/45352 , H03F2203/45354 , H03F2203/45356 , H03F2203/45366 , H03F2203/45454 , H03F2203/45471 , H03F2203/45644 , H03F2203/45648 , H03F2203/45652
摘要： PROBLEM TO BE SOLVED: To provide an OTA circuit which has high linearity with its circuit scale reduced and achieves high output current efficiency. SOLUTION: The OTA circuit comprises a first pair of transistors (M1, M2) to which a differential input signal is applied, a second pair of transistors (M3, M4) to which a common-mode voltage of the differential input signal is applied and which are parallel-connected to an output of the first pair of the transistors (M1, M2) and further whose sources are connected to each other, a third pair of transistors (M5, M6) to which the differential input signal is applied and which are cascade-connected to the second pair of the transistors (M3, M4), and a fourth pair of transistors (M5, M6) to which the differential input signal is applied and which are cascade-connected to the third pair of the transistors (M5, M8) so that input signals input to gates of the pair transistors (M7, M8) are allowed to be mutually reverse in phase. Then, common sources of the first and fourth pairs of transistors (M1, M2, M7, M8) are driven by a constant-current power supply I 0 . COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有高线性度的OTA电路，其电路规模缩小并实现高输出电流效率。解决方案：OTA电路包括施加差分输入信号的第一对晶体管（M1，M2），第二对晶体管（M3，M4），差分输入信号的共模电压并且其并联连接到第一对晶体管（M1，M2）的输出，并且其源极彼此连接;第三对晶体管（M5，M6），差分输入信号为并且与第二对晶体管（M3，M4）级联连接，并且第四对晶体管（M5，M6）被施加到差分输入信号并与第三对晶体管（M5，M8）使得输入到对晶体管（M7，M8）的栅极的输入信号被允许相位相反。然后，第一和第四对晶体管（M1，M2，M7，M8）的公共源由恒流电源I 0 驱动。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP5373088B2 Bias current generation that depends on the active time for the switched-capacitor circuit 有权
公开(公告)号：JP5373088B2
公开(公告)日：2013-12-18
申请号：JP2011527969
申请日：2009-09-17
申请人：クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人：リー、チュン・シー．
IPC分类号： H03F1/02 , H03F3/70 , H03M1/12 , H03M3/02
CPC分类号： H03F3/45183 , H03F1/0261 , H03F3/005 , H03F2203/45166 , H03F2203/45244 , H03F2203/45321 , H03F2203/45461 , H03F2203/45466 , H03F2203/45471 , H03F2203/45512 , H03F2203/45551 , H03F2203/45561 , H03F2203/45616 , H03F2203/45674
摘要： Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.

6. 发明专利

JP5133168B2 Differential amplifier circuit 有权
公开(公告)号：JP5133168B2
公开(公告)日：2013-01-30
申请号：JP2008201733
申请日：2008-08-05
申请人：ルネサスエレクトロニクス株式会社
发明人：淳嶋谷
IPC分类号： H03F3/45 , G09G3/20 , G09G3/36
CPC分类号： H03F3/45183 , H03F2200/408 , H03F2203/45466 , H03F2203/45471 , H03F2203/45512 , H03F2203/45648

7. 发明专利

JP2011528870A Low noise and high efficiency bias generation circuit and method 审中-公开
公开(公告)号：JP2011528870A
公开(公告)日：2011-11-24
申请号：JP2011518737
申请日：2009-07-17
申请人：ペレグリンセミコンダクターコーポレーション
发明人：マークイングルカーク，ロバート , ヨウンキム，タエ , ケリー，ダイラン，ジェイ
IPC分类号： H03F3/45 , H03F1/02 , H03F1/26
CPC分类号： H03F1/26 , H02M3/07 , H03F3/45183 , H03F3/45237 , H03F3/45475 , H03F3/45659 , H03F2200/453 , H03F2200/456 , H03F2200/474 , H03F2203/45138 , H03F2203/45188 , H03F2203/45366 , H03F2203/45418 , H03F2203/45424 , H03F2203/45471 , H03F2203/45642 , H03H11/245 , H03K17/145
摘要： A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an "active bias resistor" circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A threshold voltage bias voltage generation circuit may A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

8. 发明专利

JP2010041374A Differential amplifier circuit 有权
标题翻译：差分放大器电路
公开(公告)号：JP2010041374A
公开(公告)日：2010-02-18
申请号：JP2008201733
申请日：2008-08-05
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： SHIMATANI ATSUSHI
IPC分类号： H03F3/45 , G09G3/20 , G09G3/36
CPC分类号： H03F3/45183 , H03F2200/408 , H03F2203/45466 , H03F2203/45471 , H03F2203/45512 , H03F2203/45648
摘要： PROBLEM TO BE SOLVED: To improve the symmetry of output waveforms in a rising output and a falling output of a differential amplifier circuit. SOLUTION: An input stage 110 of the differential amplifier circuit 100 includes: a differential pair formed by connecting sources of an M channel MOS transistor MN1 whose gate is connected to an INM and an M channel MOS transistor MN2 whose gate is connected to an INP to each other; a constant current source IS1 connected to sources of the MN1 and the MN2; and a variable current source IS2 connected to the sources of the MN1 and the MN2. A rear-stage processing circuit comprising an intermediate stage 42 and an output stage 43 is provided with a phase compensation capacitor element C1, and performs an output following the variation of a differential input by charging and discharging the phase compensation capacitor element C1 by the constant current source IS1. The variable current source IS2 is turned on on condition that the variation of the differential input is brought ino the situation of the discharging parasitic capacitance of the source of a differential pair, and supplies a current for the discharge of the parasitic capacitance. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高差分放大器电路的上升输出和下降输出中的输出波形的对称性。
解决方案：差分放大器电路100的输入级110包括：通过连接其栅极连接到INM的M沟道MOS晶体管MN1的源极和与栅极连接的M沟道MOS晶体管MN2形成的差分对 INP彼此; 连接到MN1和MN2的源的恒流源IS1; 以及连接到MN1和MN2的源的可变电流源IS2。包括中间级42和输出级43的后级处理电路设置有相位补偿电容器元件C1，并且通过对相位补偿电容器元件C1进行充电和放电来执行差分输入的变化之后的输出。电流源IS1。可变电流源IS2在差分输入的变化导致差分对的源极的放电寄生电容的情况下被导通，并且提供用于放电寄生电容的电流。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP3847241B2 Operational amplifier 有权
公开(公告)号：JP3847241B2
公开(公告)日：2006-11-22
申请号：JP2002289073
申请日：2002-10-01
申请人： Necエレクトロニクス株式会社
发明人：信三浦
IPC分类号： H03F3/45 , H03F3/30
CPC分类号： H03F3/303 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471

10. 发明专利

JP2004519176A Circuit structure for providing exponential predistortion for the adjustable amplifier 有权
公开(公告)号：JP2004519176A
公开(公告)日：2004-06-24
申请号：JP2002570394
申请日：2002-01-30
申请人：インフィネオンテクノロジーズアクチエンゲゼルシャフト
发明人：ツァンノート，マルクス , テーゲラー，マルティン
IPC分类号： H03F1/30 , H03F1/32 , H03F3/45 , H03G7/06
CPC分类号： H03G7/06 , H03F1/3211 , H03F3/45098 , H03F2200/372 , H03F2203/45471 , H03F2203/45498 , H03F2203/45654
摘要：本発明は、可調増幅器に対して指数的な先行歪みを与えるための回路に関するものである。この可調増幅器は、２つが並列接続されている被制御回路経路を備える。この回路経路は、それぞれ、ダイオード（Ｄ１、Ｄ２）を備え、このダイオード（Ｄ１、Ｄ２）に対して、差動増幅器段（Ｔ３、Ｔ４）が直列接続されている。第２ダイオード（Ｄ１、Ｄ２）と比較した第１ダイオードの面積比率は、差動増幅器（Ｔ３、Ｔ４）の第２トランジスタ（Ｔ４）と比較した第１トランジスタ（Ｔ３）の面積比率に等しい。その結果、出力部側に供給される電流は、入力部側に入力できる制御信号と比較して、指数的な先行歪みを有する。従って、ｄＢ直線に従う増幅器を、線形で扱って制御できる。本発明の回路は、高周波技術において使用でき、プロセスパラメータ変動および温度変化の影響を非常に受けにくいことに加えて、ノイズ特性を良好にすることができる。

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