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1. 发明专利

JP4933693B2 The system and method including a wide operand architecture 有权
公开(公告)号：JP4933693B2
公开(公告)日：2012-05-16
申请号：JP2000577552
申请日：1999-08-24
申请人：マイクロユニティシステムズエンジニアリングインコーポレイテッド
发明人：クレイグハンセン , ジョンムーソーリス
IPC分类号： G06F9/34 , G06F9/38 , G06F7/38 , G06F7/48 , G06F7/483 , G06F7/499 , G06F7/52 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/318
CPC分类号： G06F9/30014 , G06F7/483 , G06F7/4991 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/30112 , G06F9/30167 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).

2. 发明专利

JPS5757361A Processing system of overflow 失效
标题翻译：溢流处理系统
公开(公告)号：JPS5757361A
公开(公告)日：1982-04-06
申请号：JP10963980
申请日：1980-08-09
申请人： Fujitsu General Ltd
发明人： IMAI TOSHIO
IPC分类号： G06F15/02 , G06F7/50 , G06F7/505
CPC分类号： G06F7/505 , G06F7/4991
摘要： PURPOSE:To eliminate the recalculation back to the first stage for an electronic computer incorporating a printer, by securing the automatic printing of the result of calculation in the operation of a specific key which is required according to the occurrence of an overflow. CONSTITUTION:When the addition key on a keyboard 4 is pushed, the contents of a figure register 1 is added with the contents of a result register 2 through an adding/subtracting circuit 8. This result of addition is checked by a deciding circuit 10. When an overflow is decided by the circuit 10, the contents of the register 1 is subtracted from the contents of the register 2 through the circuit 8 and by the overflow signal to be stored again in the register 2. At the same time, the arithmetic function is stopped. After this, a specific key on the keyboard 4 is pushed to cancel the discontinuation of the arithmetic function as well as to select the register 2. Thus the result of calculation carried out immediately before the occurrence of an overflow is printed.
摘要翻译：目的：为了消除重新计算到包含打印机的电子计算机的第一阶段，通过在根据溢出的发生所需的特定密钥的操作中确保计算结果的自动打印。构成：当按下键盘4上的加法键时，图形寄存器1的内容通过加法/减法电路8与结果寄存器2的内容相加。该判定电路10检查相加结果。当由电路10决定溢出时，通过电路8从寄存器2的内容中减去寄存器1的内容，并将溢出信号再次存储在寄存器2中。与此同时，算术功能停止此后，按下键盘4上的特定键以取消算术功能的停止以及选择寄存器2.因此，在发生溢出之前立即进行计算的结果被打印。

4. 发明专利

JP4912511B2 Speed detecting device 有权
公开(公告)号：JP4912511B2
公开(公告)日：2012-04-11
申请号：JP2011532411
申请日：2010-03-16
申请人：三菱電機株式会社
发明人：広吉川
IPC分类号： G01P3/489
CPC分类号： G01P3/489 , G01P3/481 , G06F7/4991

5. 发明专利

JP4677172B2 Device allowing processing of multiple signed independent data elements per register, method, and compiler 有权
公开(公告)号：JP4677172B2
公开(公告)日：2011-04-27
申请号：JP2002533222
申请日：2001-09-26
申请人：インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人：トレルウィズ、ジェニファー、キュー , ブラッディ、マイケル、ティー , ミッチェル、ジョーン、エル
IPC分类号： G06F9/45 , G06F7/48 , G06F7/499 , G06F9/30 , G06F9/302
CPC分类号： G06F7/4991 , G06F7/49921 , G06F7/49994 , G06F8/441 , G06F8/447 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F2207/3816 , G06F2207/3828
摘要： A compiler for data processing outputs lower-level code for packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and when executed, the code simultaneously operates on the elements in a register in a single cycle using the same operand. The elements can be independent of each other as defined by compiler directives, and the sizes of the elements in a register can differ from each other. Moreover, a relatively large element can be split across multiple registers. In an exemplary application, a data stream representing two images can be simultaneously processed using the same number of registers as have been required to process a single image. Or, a single image can be processed approaching N-times faster, where N is the number of elements per register. In any case, the present invention results in a significant increase in processing efficiency.

6. 发明专利

JPS6148036A Processing unit 失效
标题翻译：处理单元
公开(公告)号：JPS6148036A
公开(公告)日：1986-03-08
申请号：JP16931884
申请日：1984-08-15
申请人： Hitachi Ltd
发明人： SAKAI TATSUYA , ISHIKAWA SUKETAKA
IPC分类号： G06F7/38 , G06F7/00 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/494 , G06F7/50 , G06F7/76
CPC分类号： G06F7/494 , G06F7/4991 , G06F2207/3828 , G06F2207/4924
摘要： PURPOSE:To obtain a high-speed N-ary operation overflow detecting means by detecting an overflow in the case where an effective data included in an N-ary operation result is larger than a result storing region in accordance with an effective data most significant position indicating value obtained from the N-ary operation and a value showing the length of the result storing region. CONSTITUTION:An overflow decision circuit 13 carries out a logical operation of OVF=OV0+OV1+CAR.(S1+S2+A). Herein, (S1+S2+A) indicates a conditional expression showing that a decimal adder carries out addition between the same code data. CAR.(S1+S2+A) shows that when the addition between the same code data is performed, there is a carry CAR from a top bit of a binary adder. When any one of first and second operands exceeds 8 byte, initially, the operation of the latter half of 8 byte is carried out. At that time, CAR is not given to the overflow decision circuit 13 but used during the addition of the other byte carried out in the next place through a bus fed to a least significant bit of the binary adder 2.
摘要翻译：目的：通过在N运算结果中包含的有效数据大于根据有效数据最高有效位置的结果存储区域的情况下检测溢出来获得高速N运算溢出检测装置指示从N运算操作获得的值和表示结果存储区域的长度的值。构成：溢出判定电路13执行OVF = OV0 + OV1 + CAR（S1 + S2 + A）的逻辑运算。这里，（S1 + S2 + A）表示表示十进位加法器在相同代码数据之间执行加法的条件表达式。 CAR（S1 + S2 + A）表示当执行相同代码数据之间的相加时，存在来自二进制加法器的顶部位的进位CAR。当第一和第二操作数中的任何一个超过8字节时，最初执行8字节后半部分的操作。此时，不向溢出判定电路13给出CAR，而是在通过馈送到二进制加法器2的最低有效位的总线的下一次执行的另一字节的加法期间使用CAR。

7. 发明专利

JPS59117637A Floating point multiplier 失效
标题翻译：浮动点乘法器
公开(公告)号：JPS59117637A
公开(公告)日：1984-07-07
申请号：JP22800282
申请日：1982-12-24
申请人： Toshiba Corp
发明人： YAGUCHI TOSHIYUKI , KANUMA AKIYOSHI , TAMARU KIICHIROU
IPC分类号： G06F7/487 , G06F7/00 , G06F7/508 , G06F7/52 , G06F7/76
CPC分类号： G06F7/4876 , G06F7/4991
摘要： PURPOSE: To execute the floating point multiplication of IEEE standard with one adder, by correcting the input or the output of an exponential part adder.
CONSTITUTION: The multiplication is executed by adding an exponential part in an adder ALU. The floating point multiplication of IEEE standard is expressed with a form of the subtraction of a base B from addition of inputs X and Y. The subtraction of the base B from the operand X is attained by the addition of the operand X and the complement of the base B, and in this case, necessity of carry occurs in the addition result in accordance with the state of the most significant bit MSB of the operand X. The operation between the operand X and the base B is terminated by considering carry with respect to the inverted result of the MSB of the operand X in an inverter 103. Consequently, the operand X is corrected by the inverter 103 and is inputted to an ALU101, and the operand Y is inputted as it is, thus terminating the multiplication.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过一个加法器执行IEEE标准的浮点乘法，通过校正指数部分加法器的输入或输出。构成：通过在加法器ALU中添加指数部分来执行乘法。 IEEE标准的浮点乘法以从输入X和Y的加法中减去基数B的形式表示。通过添加操作数X和操作数X的补码，可以从操作数X中减去基数B 基本B，并且在这种情况下，根据操作数X的最高有效位MSB的状态在相加结果中发生进位的必要性。操作数X与基准B之间的操作通过考虑到反转器103中的操作数X的MSB的反相结果。因此，操作数X被逆变器103校正并被输入到ALU101，并且操作数Y被原样输入，从而终止乘法。

8. 发明专利

JP2004013519A Arithmetic method and arithmetic circuit 有权
公开(公告)号：JP2004013519A
公开(公告)日：2004-01-15
申请号：JP2002166018
申请日：2002-06-06
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： UEHARA TERUAKI , ISHIDA KEITARO
IPC分类号： G06F7/00 , G06F7/38 , G06F7/499 , G06F7/50 , G06F7/509 , G06F7/60
CPC分类号： G06F7/5095 , G06F7/4991 , G06F7/607
摘要： PROBLEM TO BE SOLVED: To provide an arithmetic method and circuit for enlarging the dynamic range of a register on a processor. SOLUTION: This arithmetic method comprises a procedure for executing the arithmetic operation of a processor by an arithmetic unit 4 and an accumulator 1, a procedure for combining the contents of an up/down counter 5 with the contents of the accumulator 1 regularly corresponding to the carry signal of the arithmetic unit 4 and the code signal of input data from a data bus 2 to the arithmetic unit 4, and for outputting a control signal to control it to be turned into a correct value to the up/down counter 5, a procedure for outputting the value of the accumulator 1 to the data bus 2 and the arithmetic unit 4 by the accumulator 1, and a procedure for outputting the value of the up/down counter 5 having the value of the high-order part of the correct value beyond the allowable range of the accumulator 1 to the data bus 2 by the up/down counter 5. COPYRIGHT: (C)2004,JPO

9. 发明专利

JPS59174971A Data summing-up system 失效
标题翻译：数据汇总系统
公开(公告)号：JPS59174971A
公开(公告)日：1984-10-03
申请号：JP4875883
申请日：1983-03-25
申请人： Casio Comput Co Ltd
发明人： TSUZUKI HANZOU
IPC分类号： G06F7/38 , G06F7/50 , G06F7/508 , G06F7/509 , G07G1/12
CPC分类号： G06F7/5095 , G06F7/4991
摘要： PURPOSE:To obtain correct data by summing up overflowing data of high order position in a previously appointed storage area when data overflow from a summing device which stores an accumulated value. CONSTITUTION:Data accumulated in a departmental sum memory 3 and extended memory 4 based on a departmental registration, are printed on a recording paper at the time of inspection and adjustment of account. In this case, when the content of the memory 3 is separately read out departmentally at the time of inspection and adjustment of account, it is discriminated whether addresses for extension are stored in areas Q and S of pertinent departments or not. When the addresses are stored, data in the memory 4 indicated by the addresses are first printed, and then, data in the memory 3 are printed. Therefore, even when data overflow from the summing device of the departmental sum memory 3, overflowing high order position data are also printed and correct data can be obtained.
摘要翻译：目的：通过对来自存储累加值的求和装置的数据溢出的先前指定的存储区域中的高位置的溢出数据进行求和来获得正确的数据。规定：根据部门登记在部门总存储器3和扩展存储器4中累积的数据在检查和调整帐户时被印在记录纸上。在这种情况下，当在检查和调整帐户时单独地读出存储器3的内容时，判断扩展地址是否存储在相关部门的区域Q和S中。当存储地址时，首先打印由地址指示的存储器4中的数据，然后打印存储器3中的数据。因此，即使当从总和存储器3的求和装置发生数据溢出时，即使打印出溢出的高位置数据，也可以得到正确的数据。

10. 发明专利

JPS59174942A Arithmetic control device 失效
标题翻译：算术控制装置
公开(公告)号：JPS59174942A
公开(公告)日：1984-10-03
申请号：JP4992983
申请日：1983-03-25
申请人： Toshiba Corp
发明人： EGUCHI KAZUTOSHI
IPC分类号： G06F7/00 , G06F7/50 , G06F7/505 , G06F7/76
CPC分类号： G06F7/505 , G06F7/4991 , G06F2207/3816
摘要： PURPOSE:To prevent redundant calculation and to improve the practical arithmetic processing speed of a variable-length data, by checking the number of effective figures of the 2nd operand and performing the precheck of overflow by using the checked result. CONSTITUTION:An Reg II (the number of effective figures of the 2nd operand) selected by a selector 33 and an L1*2 (which is obtained by shifting L1 data leftward by one bit) selected by another selector 34 are inputted into an adder- subtracter 35. When the subtraction result of L1*2-Reg II is 0 (zero) or negative, it is judged that overflow occurs. In case where it is judged that overflow occurs, the calculation is not executed by a calculating section and a condition code indicating overflow is produced by treating the calculation as processing- terminated one. On the other hand, when no overflow is judged as a result of the calculation, arithmetic of (the 1st operand + one digit) is executed by the arithmetic section.
摘要翻译：目的：为了防止冗余计算并提高可变长度数据的实际算术处理速度，通过使用检查结果检查第二个操作数的有效数字并执行溢出预检。构成：由选择器33选择的寄存器II（第二操作数的有效数字）和由另一个选择器34选择的将L1数据向左移位一位的L1 * 2输入到加法器 - 减法器35.当L1 * 2-Reg II的减法结果为0（零）或否定时，判断为溢出。在判定发生溢出的情况下，计算部分不执行计算，通过将计算作为处理终止处理来生成表示溢出的条件代码。另一方面，当作为计算的结果未判断溢出时，由运算部执行（第1操作数+ 1位）的运算。

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