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1. 发明专利

JPS6373473A BUTTERFLY ARITHMETIC CIRCUIT 失效
公开(公告)号：JPS6373473A
公开(公告)日：1988-04-04
申请号：JP21843686
申请日：1986-09-17
申请人： TOSHIBA CORP
发明人： YAGUCHI TOSHIYUKI
IPC分类号： G06F17/14 , F02B75/02
摘要： PURPOSE:To shorten the time required for butterfly arithmetic of 1/2 word length by adopting the constitution of both a multiplier and an ALU that can divide arithmetic into high-order and low-order bits. CONSTITUTION:At the time of arithmetic mode of 1/2 word length data a multiplier MPY and arithmetic circuits ALU1 and 2 divide their arithmetic operations into high-order n/2 bits XH and YH and low-order n/2 bits XL and YL respectively. In other words, the high-order n/2 bits of XH.YH are inputted to the most significant n/2 bit of the multiplication result 2n of the multiplier MPY together with the high-order n/2 bits of XL.YL inputted to the next n/2 bit, the low-order n/2 bits of XH.YH inputted to the following n/2 bit, and the low-order n/2 bits of XL.YL inputted to the least significant n/2 bit respectively. In the circuits ALU1 and 2 the arithmetic result of XH.YH is inputted to the high-order n/2 bit of the arithmetic (n) bits together with the arithmetic result of XL.YL supplied to the low-order n/2 bit respectively. Thus it is possible to carry out the butterfly arithmetic of 1/2 word length in a 1-butterfly/2-cycle way and therefore to shorten the butterfly arithmetic time.

2. 发明专利

JP2004021932A Data location converter 审中-公开
公开(公告)号：JP2004021932A
公开(公告)日：2004-01-22
申请号：JP2002180293
申请日：2002-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMIYAMA HIDEOMI , AKEMI KAZUHIRO , YAGUCHI TOSHIYUKI
IPC分类号： G06F12/02
摘要： PROBLEM TO BE SOLVED: To omit an alignment process of pieces of data in a CPU, and provide high speed calculation and a high speed rearranging process or the like of the pieces of data in the CPU.
SOLUTION: The data location converter is disposed between the CPU capable of processing data in parallel and a memory storing predetermined data in each address. It is provided with an address comparator comparing address signals inputted from the CPU and outputting a rearrangement control signal when particular addresses are assigned, a memory control part reading a plurality of pieces of data stored in the addresses when the rearrangement control signal is supplied and controlling the pieces of data read from the assigned addresses of the memory along with their addresses, and a rearranging process part executing a realignment process of data by address rearrangement and predetermined calculation to the plurality of pieces of data read from the assigned addresses of the memory via the memory control part on the basis of the rearrangement control signal.
COPYRIGHT: (C)2004,JPO

3. 发明专利

JPH08101820A MICROPROCESSOR 失效
公开(公告)号：JPH08101820A
公开(公告)日：1996-04-16
申请号：JP23780394
申请日：1994-09-30
申请人： TOSHIBA CORP
发明人： FUJIMURA HIRONORI , YAGUCHI TOSHIYUKI
IPC分类号： G06F1/32 , G06F9/30 , G06F15/78
摘要： PURPOSE: To make a circuit not operate at a data pass part and reduce the power consumption by keeping on supplying a control signal which is supplied so far to the data pass part when no operation is performed mat the data pass part. CONSTITUTION: When no operation is performed at the data pass part 4 (at NOP time), a signal CC=0 is inputted as the control signal of a latch 12 according to the decoding result of an instruction by an instruction decoding part 1, so the C latch performs no latching operation. Consequently, the instruction decoding part 1 outputs control signals CLI and CLO=0 so that neither of output latches 5 and 7 performs latching operation while the control signal CO=A is outputted to the data pass part 4. Therefore, the input data DI and control signal CO never change at the data pass part 4, so no switching is done. Consequently, when the data pass part 4 performs no operation, the data pass part 4 does not operate and the power consumption is reducible.

4. 发明专利

JPH02299337A BUS CONSTITUTION SUITABLE FOR DATA COMMUNICATION 失效
公开(公告)号：JPH02299337A
公开(公告)日：1990-12-11
申请号：JP12015189
申请日：1989-05-13
申请人： TOSHIBA CORP
发明人： KATSUMATA HIDEKAZU , TANAKA KOICHI , YAGUCHI TOSHIYUKI , NISHIKAWA TETSUTO , KANUMA AKIYOSHI
IPC分类号： G06F13/36 , G06F13/00 , G06F13/28 , G06F13/40 , H04L29/02
摘要： PURPOSE:To quicken the data transfer by connecting directly a port 1 of a 2-port memory to at least a microprocessor and a DMA. CONSTITUTION:When a data reception command is sent to an SBI 60 via a system bus SB and sent further to a microprocessor 20, the received data is sent to an NBI 10 via a network bus NB and a bus B9 and sent to the port 1 of a 2-port memory 70 via a bus B4. The 2-port memory 70 rearranges the received data according to the control of the microprocessor 20 and a control logic circuit section 80 receiving the reception command, the rearranged reception data is outputted from a port 2 and sent to the system bus SB via the DMA 50 and the SBI 60.

5. 发明专利

JPH02206772A TEST FACILITATING CIRCUIT 失效
公开(公告)号：JPH02206772A
公开(公告)日：1990-08-16
申请号：JP2659389
申请日：1989-02-07
申请人： TOSHIBA CORP
发明人： YAGUCHI TOSHIYUKI , TANAKA KOICHI
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
摘要： PURPOSE:To efficiently input and output the storage contents, and to easily and quickly execute independence of a function block and a combination test of the block by scanning each separate group register of every function block, and also, controlling an output and an input. CONSTITUTION:Shift registers 111 - 114, 121 - 124 of every group of a block 1 through a function circuit 11 and an input/output control circuit 12 of a function block 1, and shift registers 141 - 144, 131 - 134 of every group by a combination of the blocks 1, 2 are scanned by the corresponding internal scan buses IB 2, 4 and 6. An input and an output based on this scan are controlled by tri-state buffers P11 - P14 controlled by a decoder 30. The block 2 brought to scan control independently from the block 1 is also the same, and an input and an output of the storage contents are executed efficiently.

6. 发明专利

JPS61218962A LOGIC CIRCUIT 失效
公开(公告)号：JPS61218962A
公开(公告)日：1986-09-29
申请号：JP6120285
申请日：1985-03-26
申请人： TOSHIBA CORP
发明人： YAGUCHI TOSHIYUKI , KANUMA AKIYOSHI
IPC分类号： G06F11/22 , G01R31/28
摘要： PURPOSE:To test easily a logical function by reading data on a circuit, which is connected to the prescribed node of a combined circuit and holds the logical state of the node, and monitoring the node of the combined circuit. CONSTITUTION:At the time of testing the logical function, a latch signal phiL is outputted in the prescribed timing when the data is held, and the states of the nodes N1-N3 are maintained in data holding circuits L11-L3n. Afterward, a data transfer clock DTXCK 1 is outputted, and the maintained data is sequentially transferred to the circuits L11-L3n, and outputted by one bit as monitor data Dmon through a common bus B. In such a way the inner node logical state in the large-scaled combined circuit is read out from the outside, and a defective part is detected with the aid of the data, thereby conducting easily the logical function test.

7. 发明专利

JPH03167487A TEST FACILITATING CIRCUIT 失效
公开(公告)号：JPH03167487A
公开(公告)日：1991-07-19
申请号：JP30644289
申请日：1989-11-28
申请人： TOSHIBA CORP
发明人： YAGUCHI TOSHIYUKI
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C29/00 , G11C29/14 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PURPOSE:To enhance test efficiency by mounting an input/output means performing initial setting of the memory part within a first main module and reading the data from the memory part and a usual operation means usually operating a common bus control circuit and the memory part. CONSTITUTION:When TMOD is set at a level 1 through a test mode control wire lT and a test mode is set, usual operation is stopped. Next, the common bus control data to an instruction register (IR)1c through a test I/O control wire l1 is set. Subsequently, the address of the memory part 4a or 5a of a reading destination is written in an address register (AR)1d through the control wire l1. Next, SICLK is set at a level 1 through a usual operation control wire lS. By this constitution, the data of the memory part indicated by the address in the AR1d is read in a data register (DR)1e through a common bus 40. Finally, the data of the DR1e is read from the control wire l1.

8. 发明专利

JPH01227973A TEST FACILITATING CIRCUIT 失效
公开(公告)号：JPH01227973A
公开(公告)日：1989-09-12
申请号：JP5375388
申请日：1988-03-09
申请人： TOSHIBA CORP
发明人： YAGUCHI TOSHIYUKI
IPC分类号： G01R31/317 , G01R31/28 , G06F11/22
摘要： PURPOSE:To make a testing time shorter by comparing optional output data of plural functional circuits to which input test signals are given with the values of the circuits at the time of normal operation and, at the same time, collating whether or not the optional output data are coincident with the data of other functional circuits. CONSTITUTION:Input test data TD selected at the time of testing operation are given to (m) pieces of functional circuits T1, Tm and the circuits T1,-,Tm respectively output N-bit output data. In such state, the output data of an optional functional circuit T1 are compared with the values of the circuit T1 at the time of normal operation and, when they coincide with each other, it is confirmed that the circuit T1 normally operates. Then the exclusive OR gate of a discriminating section takes the exclusive OR of the output data of each functional circuit and, when it is discriminated that all of the output data are the same from the calculated results, normal operations of all functional circuits are confirmed. Therefore, the testing time can be shortened.

9. 发明专利

JPS6244674A EVALUATION FACILITATING CIRCUIT 失效
公开(公告)号：JPS6244674A
公开(公告)日：1987-02-26
申请号：JP18404085
申请日：1985-08-23
申请人： TOSHIBA CORP
发明人： YAGUCHI TOSHIYUKI
IPC分类号： G01R31/28 , G01R31/3177
摘要： PURPOSE:To easily check respective nodes and to improve the degree of integration by holding node levels of respective logic circuits in latch circuits in an array. CONSTITUTION:Levels of respective nodes of a logic circuit to be checked which are connected to an evaluation facilitating circuit 3 are received through plural data lines D11-Dnm and held in arrayed latch circuits of a data holding circuit 5 according to a data holding signal WE from the data holding and transfer control circuit 7 of the circuit 3. The held contents are read out and outputted by a circuit 7 which reacts to an external address and a check is not made direction by using a tester, so the respective nodes are easily checked. Further, the degree of integration is improved by this array latch constitution and the evaluation facilitating circuit is reduced in size.

10. 发明专利

JPS59117637A Floating point multiplier 失效
标题翻译：浮动点乘法器
公开(公告)号：JPS59117637A
公开(公告)日：1984-07-07
申请号：JP22800282
申请日：1982-12-24
申请人： Toshiba Corp
发明人： YAGUCHI TOSHIYUKI , KANUMA AKIYOSHI , TAMARU KIICHIROU
IPC分类号： G06F7/487 , G06F7/00 , G06F7/508 , G06F7/52 , G06F7/76
CPC分类号： G06F7/4876 , G06F7/4991
摘要： PURPOSE: To execute the floating point multiplication of IEEE standard with one adder, by correcting the input or the output of an exponential part adder.
CONSTITUTION: The multiplication is executed by adding an exponential part in an adder ALU. The floating point multiplication of IEEE standard is expressed with a form of the subtraction of a base B from addition of inputs X and Y. The subtraction of the base B from the operand X is attained by the addition of the operand X and the complement of the base B, and in this case, necessity of carry occurs in the addition result in accordance with the state of the most significant bit MSB of the operand X. The operation between the operand X and the base B is terminated by considering carry with respect to the inverted result of the MSB of the operand X in an inverter 103. Consequently, the operand X is corrected by the inverter 103 and is inputted to an ALU101, and the operand Y is inputted as it is, thus terminating the multiplication.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过一个加法器执行IEEE标准的浮点乘法，通过校正指数部分加法器的输入或输出。构成：通过在加法器ALU中添加指数部分来执行乘法。 IEEE标准的浮点乘法以从输入X和Y的加法中减去基数B的形式表示。通过添加操作数X和操作数X的补码，可以从操作数X中减去基数B 基本B，并且在这种情况下，根据操作数X的最高有效位MSB的状态在相加结果中发生进位的必要性。操作数X与基准B之间的操作通过考虑到反转器103中的操作数X的MSB的反相结果。因此，操作数X被逆变器103校正并被输入到ALU101，并且操作数Y被原样输入，从而终止乘法。

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