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1. 发明专利

JPS61138334A Decimal arithmetic processor 失效
标题翻译：十进制算术处理器
公开(公告)号：JPS61138334A
公开(公告)日：1986-06-25
申请号：JP25996384
申请日：1984-12-11
申请人： Toshiba Corp
发明人： HORIUCHI MASAO
IPC分类号： G06F7/494 , G06F7/02 , G06F7/38 , G06F7/496 , G06F7/50 , G06F7/506
CPC分类号： G06F7/494 , G06F2207/3828 , G06F2207/4924
摘要： PURPOSE:To improve the numeric expression capability by about 1/2 digit in comparison with a conventional device to improve the efficiency of a memory area where decimal data is stored, by applying decimal data in a new data format having the complement expression where the most significant digit is a data digit used for numeric value as well as sign. CONSTITUTION:When subtraction is designated, signal '1' from a CPU is inputted to an FF55. Minuend and subtrahend data are loaded to registers R1 and R2 respectively. Subtrahend data is subtracted from fixed value '9916' by a subtractor 51, and the result is set to a register R3. Contents of registers R1 and R3 and the FF55 are added, and the result is loaded to registers R4 and R5. The exclusive or between contents of registers R1 and R3 is operated by a means 59 and is loaded to a register R6, and the exclusive OR between the addition result of contents of the register R5 and '6616' and contents of the register R6 is operated by the means 59, and the AND between this result and '11016' is operated by a means 60 to obtain an intermediate result Q1. The intermediate result Q1 is divided by '1016', and the result is multiplied by '616' to obtain an intermediate result Q2. The intermediate result Q2 and contents of the register R4 are added, and the addition result is loaded to a shift register SR and is sent to the CPU through a bus 43.
摘要翻译：目的：为了提高数字表达能力，与常规设备相比，提高约1/2位数，以提高存储十进制数据的存储区域的效率，通过以补码表达式最多的新数据格式应用十进制数据有效数字是用于数值和符号的数据数字。构成：当指定减法时，来自CPU的信号“1”被输入到FF55。 Minuend和subtrahend数据分别加载到寄存器R1和R2。通过减法器51从固定值“9916”中减去子纹理数据，并将结果设置为寄存器R3。添加寄存器R1，R3和FF55的内容，结果加载到寄存器R4和R5。寄存器R1和R3的异或内容由装置59操作并被加载到寄存器R6，并且寄存器R5的内容的相加结果和“6616”的内容与寄存器R6的内容之间的异或运算通过装置59，并且该结果与'11016'之间的AND由装置60操作以获得中间结果Q1。将中间结果Q1除以'1016'，结果乘以'616'，得到中间结果Q2。添加中间结果Q2和寄存器R4的内容，并将相加结果加载到移位寄存器SR，并通过总线43发送到CPU。

2. 发明专利

JPS5957342A Decimal adder 失效
标题翻译： DECIMAL ADDER
公开(公告)号：JPS5957342A
公开(公告)日：1984-04-02
申请号：JP16748282
申请日：1982-09-28
申请人： Nec Corp
发明人： TANAKA KAZUMASA
IPC分类号： G06F7/494 , G06F7/50 , G06F7/508
CPC分类号： G06F7/494 , G06F2207/4922 , G06F2207/4924
摘要： PURPOSE:To improve the processing speed by executing a correcting phase in the same cycle as the phase of intermediate sum for the addition being the 2nd and succeeding, in executing the accumulative addition of plural binary coded decimal numbers by means of 3-input binary adders. CONSTITUTION:In executing the accumulative addition of n-set of decimal numbers Di, values D1, D2 are set respectively to registers 2, 3, intermediate sums S0-S3 outputted from the adder 1 are set to the register 2 in the 1st addition phase, carry outputs C0-C3 of each digit are set to a holding register 5 and the next value D3 is set to the register 3. The intermediate sum of the (i-1)th addition from the register 2 in the i-th adder is applied to the 1st input of the register 3, a value Di+1 is applied to the 2nd input from the register 3, (0) is applied to a CIN input, and (0) or (6) is selected at each digit depending on the content of the register 5 and applied to the 3rd input. In the final correcting phase, 0000 is applied to the 2nd input from the register 3, (1) is applied to the CIN input and the selecting circuit 4 selects (9) or F and applies it to the 3rd input.
摘要翻译：目的：为了通过在相加周期的相位周期内执行校正相位来提高处理速度，该相位是相加的第二和后续的相位，在执行通过3输入二进制加法器累积添加多个二进制编码的十进制数。构成：在执行n组十进制数Di的累积加法时，将值D1，D2分别设置为寄存器2,3，从加法器1输出的中间和S0-S3在第1加法相位中被设定为寄存器2 ，每个数字的进位输出C0-C3被设置到保持寄存器5，下一个值D3被设置为寄存器3.从第i个加法器中的寄存器2的第（i-1）个相加的中间和被应用于寄存器3的第一输入，从寄存器3向第二输入端施加值Di + 1，（0）被施加到CIN输入，并且在每个数字处选择（0）或（6）取决于寄存器5的内容并应用于第3个输入。在最终校正阶段，将0000应用于寄存器3的第二输入，（1）施加于CIN输入，选择电路4选择（9）或F并将其应用于第3输入。

3. 发明专利

JPS6148036A Processing unit 失效
标题翻译：处理单元
公开(公告)号：JPS6148036A
公开(公告)日：1986-03-08
申请号：JP16931884
申请日：1984-08-15
申请人： Hitachi Ltd
发明人： SAKAI TATSUYA , ISHIKAWA SUKETAKA
IPC分类号： G06F7/38 , G06F7/00 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/494 , G06F7/50 , G06F7/76
CPC分类号： G06F7/494 , G06F7/4991 , G06F2207/3828 , G06F2207/4924
摘要： PURPOSE:To obtain a high-speed N-ary operation overflow detecting means by detecting an overflow in the case where an effective data included in an N-ary operation result is larger than a result storing region in accordance with an effective data most significant position indicating value obtained from the N-ary operation and a value showing the length of the result storing region. CONSTITUTION:An overflow decision circuit 13 carries out a logical operation of OVF=OV0+OV1+CAR.(S1+S2+A). Herein, (S1+S2+A) indicates a conditional expression showing that a decimal adder carries out addition between the same code data. CAR.(S1+S2+A) shows that when the addition between the same code data is performed, there is a carry CAR from a top bit of a binary adder. When any one of first and second operands exceeds 8 byte, initially, the operation of the latter half of 8 byte is carried out. At that time, CAR is not given to the overflow decision circuit 13 but used during the addition of the other byte carried out in the next place through a bus fed to a least significant bit of the binary adder 2.
摘要翻译：目的：通过在N运算结果中包含的有效数据大于根据有效数据最高有效位置的结果存储区域的情况下检测溢出来获得高速N运算溢出检测装置指示从N运算操作获得的值和表示结果存储区域的长度的值。构成：溢出判定电路13执行OVF = OV0 + OV1 + CAR（S1 + S2 + A）的逻辑运算。这里，（S1 + S2 + A）表示表示十进位加法器在相同代码数据之间执行加法的条件表达式。 CAR（S1 + S2 + A）表示当执行相同代码数据之间的相加时，存在来自二进制加法器的顶部位的进位CAR。当第一和第二操作数中的任何一个超过8字节时，最初执行8字节后半部分的操作。此时，不向溢出判定电路13给出CAR，而是在通过馈送到二进制加法器2的最低有效位的总线的下一次执行的另一字节的加法期间使用CAR。

4. 发明专利

JPS5177046A Sanjutsuenzanhohooyobisonodeetapuroseshingushisutemu 失效
公开(公告)号：JPS5177046A
公开(公告)日：1976-07-03
申请号：JP14125975
申请日：1975-11-27
申请人： Signetics Corp
发明人： DABIDO RAARII ZEMERU , ROBAATO JERARUDO KAAKU
IPC分类号： G06F7/494 , G06F7/50 , G06F7/508
CPC分类号： G06F7/494 , G06F2207/3828 , G06F2207/4924

5. 发明专利

JPS6133540A Decimal adding/subtracting device 失效
标题翻译：十进制加/减设备
公开(公告)号：JPS6133540A
公开(公告)日：1986-02-17
申请号：JP15482284
申请日：1984-07-25
申请人： Nec Corp
发明人： TAKAHASHI TOSHIYA
IPC分类号： G06F7/494 , G06F7/50 , G06F7/508
CPC分类号： G06F7/494 , G06F2207/4924
摘要： PURPOSE:To execute decimal arithmetic having many digits at a high speed and to detect incorrect data simultaneously by executing decimal addition/subtraction only by one use of a binary adder/subtractor. CONSTITUTION:Registers 201, 202 store operand data to be required at a decimal operation time and its decimal arithmetic result is stored in a register 207. Data stored in the register 201 are inputted through an A line and whether the data are valid or not as a binary-coded decimal number (BCD) is discriminated by an invalid data detecting circuit 203. A compensating circuit 204 discriminates whether data stored in the register 202 are valid or not as a BCD and adds ''0110'' to all digits of the input data. Thus, the data obtained from C and D lines are inputted to a binary adder/subtractor 205 and the added/subtracted result is outputted to a line for binary addition/subtraction. A post-compensating circuit 206 compensates data on an E line by the carry information obtained from the binary adder/subtractor 205.
摘要翻译：目的：执行高速数位的十进制运算，并通过一次使用二进制加法器/减法器执行加减运算来同时检测不正确的数据。构成：201,202的寄存器存储十进制运算时所需要的运算数据，其十进制运算结果存储在寄存器207中。存储在寄存器201中的数据通过A线输入，数据是否有效二进制编码的十进制数（BCD）由无效数据检测电路203鉴别。补偿电路204鉴别存储在寄存器202中的数据是否有效，作为BCD，并将“0110”加到“ 输入数据。因此，将从C和D线获得的数据输入到二进制加法器/减法器205，并将加/减结果输出到用于二进制加/减的行。后补偿电路206通过从二进制加法器/减法器205获得的进位信息来补偿E线上的数据。

6. 发明专利

JPS59170938A Decimal adder/subtractor 失效
标题翻译： DECIMAL ADDER / SUBTRACTOR
公开(公告)号：JPS59170938A
公开(公告)日：1984-09-27
申请号：JP4518183
申请日：1983-03-17
申请人： Nec Corp
发明人： YAGIHASHI TOSHIO
IPC分类号： G06F7/494 , G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/494 , G06F2207/3828 , G06F2207/4924
摘要： PURPOSE:To shorten instruction executing time and to improve the performance of the titled circuit by adding/subtracting a 9-bit byte pack type decimal number as the 9-bit byte format without data conversion from 9 bits to 8 bits. CONSTITUTION:The adder/subtractor 9 receives the output of a selecting circuit 6 as a left input through a signal line 102 and the output of a selecting circuit 7 as a right input through a signal line 103 to add/subtract a 9-bit byte pack type decimal number. The decimal adder/subtractor 9 is constituted by a decimal adder/subtractor group 20-1-20-8 for 4 bits, a binary adder group 21-1-21-4 for one bit which receive the uppermost bit of each 9-bit byte as the 1st input and the inverted output of the uppermost bit as the 2nd input and a carrying foresight circuit 22. A carrying generating output and a carrying transmitting output from the binary adder group 21 and the decimal adder/subtractor group 20 are inputted to the carrying foresight circuit 22 to form a carrying input to the decimal adder/subtractor group 20. A ''0'' coupling circuit 10 couples ''0'' with the upper one bit of each 8-bit byte output from the adder/subtractor 9.
摘要翻译：目的：缩短指令执行时间，并通过将9位字节数据包类型的十进制数字作为9位字节格式加/减，从而将数据从9位转换为8位，从而提高了标题电路的性能。构成：加法器/减法器9通过信号线102接收选择电路6的输出，作为左输入，通过信号线103将选择电路7的输出作为右输入，以加/减9位字节包类型十进制数。十进制加减法器9由4位的十进制加减法器组20-1-20-8构成，一位接收每9位的最高位的二进制加法器组21-1-21-4 字节作为第一输入，最高位的反相输出作为第二输入和载入前视电路22.来自二进制加法器组21和十进制加减法器组20的承载产生输出和载运发送输出被输入到携带的前视电路22形成到十进制加减法器组20的输入输入。“0”耦合电路10将“0”与从加法器/减法器组20输出的每个8位字节的高位比较“0” 减法器9。

7. 发明专利

JPS593633A Decimal arithmetic device 失效
标题翻译：十进制算术设备
公开(公告)号：JPS593633A
公开(公告)日：1984-01-10
申请号：JP11417382
申请日：1982-06-30
申请人： Nec Corp
发明人： OOISHI HIROMI
IPC分类号： G06F7/494 , G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/494 , G06F2207/3828 , G06F2207/4924
摘要： PURPOSE:To eliminate the need for a format converter and to shorten an arithmetic processing time, by processing two kinds of data, i.e. packed data and unpacked data without converting decimal data from an unpacked format to a packed format. CONSTITUTION:A means for processing two kinds of data, i.e. packed and unpacked data without converting unpacked decimal data into packed data is provided. For example, the low-order two digits of an operand are inputted to a device 100 which receives the 1st operand and a device 101 which receives the 2nd operand, and the zone part of the output of the device 100 is corrected into a specific constant by selecting devices 102a and 102b on the basis of the data format and information from an arithmetic mode display device 105. The corrected value from the selecting devices 102a and 102b and the output of the device 101 are processed by decimal computing elements 104b and 104d, and a zone code is inserted into zone parts of their outputs by selecting circuits 103a and 103b on the basis of information from a data format display device 106.
摘要翻译：目的：为了消除对格式转换器的需要并缩短算术处理时间，通过处理两种数据，即打包数据和未打包数据，而不将十进制数据从未打包格式转换为打包格式。规定：提供了处理两种数据的方法，即打包和解包的数据，而不将未打包的十进制数据转换为打包数据。例如，操作数的低位两位数被输入到接收第一操作数的装置100和接收第二操作数的装置101，将装置100的输出的区域部分修正为特定常数通过根据来自算术模式显示装置105的数据格式和信息来选择装置102a和102b。来自选择装置102a和102b的校正值和装置101的输出由十进制计算元件104b和104d处理，并且基于来自数据格式显示装置106的信息，通过选择电路103a和103b将区码插入其输出的区域部分。

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