专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

2. 发明专利

JP2014041474A Multiplication device and multiplication method 有权
标题翻译：多媒体设备和多路复用方法
公开(公告)号：JP2014041474A
公开(公告)日：2014-03-06
申请号：JP2012183419
申请日：2012-08-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KITAMURA KENICHI
IPC分类号： G06F7/483 , G06F7/52
CPC分类号： G06F5/012 , G06F7/485 , G06F7/4876
摘要： PROBLEM TO BE SOLVED: To provide a multiplication device capable of performing the multiplication of a floating point number.SOLUTION: A multiplication device includes: a circuit (904) for counting the number of zero continuous to the high order of the mantissa part of a multiplier; a circuit (906) for calculating shift amounts on the basis of the number of digits of the fixing accuracy of the mantissa part and the counted value; a circuit (905) for left-shifting the mantissa part of the floating point number as a multiplicand only by the shift amounts; circuits (906, 913) for calculating the number of digits of the mantissa part of the multiplier by subtracting the counted value from the number of digits of the fixing accuracy of the mantissa part; a multiplication circuit (915) for outputting an intermediate product by the digit units of the mantissa part of the multiplier on the basis of the left-shifted mantissa part of the multiplicand and the mantissa part of the multiplier; an addition circuit (902) for adding the exponent parts of the multiplicand and multiplier; and a control circuit (918) for outputting the intermediate product output by the multiplication circuit as the mantissa part of the floating point number of a product, and for outputting the value output by the addition circuit as the exponent part of the floating point number of the product.
摘要翻译：要解决的问题：提供一种能够执行浮点数乘法运算的乘法装置。解码器：乘法装置包括：电路（904），用于对与a的尾数部分的高次数连续的零数进行计数乘数; 用于根据尾数部分的定影精度和计数值的位数计算移位量的电路（906）; 用于将浮点数的尾数部分左移至被乘数的电路（905）除以移位量; 电路（906,913），用于通过从尾数部分的定影精度的位数减去计数值来计算乘数的尾数部分的位数; 乘法电路（915），用于根据乘法器的左移尾数部分和乘法器的尾数部分，通过乘数的尾数部分的数字单位输出中间乘积; 加法电路（902），用于将乘法器和乘法器的指数部分相加; 以及控制电路（918），用于将由乘法电路输出的中间乘积作为乘积的浮点数的尾数部分输出，并将由加法电路输出的值作为浮点数的指数部分输出该产品。

3. 发明专利

JP5400197B2 Large multiplier for the programmable logic device 有权
公开(公告)号：JP5400197B2
公开(公告)日：2014-01-29
申请号：JP2012172915
申请日：2012-08-03
申请人：アルテラコーポレイションAltera Corporation
发明人：ラングハマーマーティン , サーマリンガムクマラ
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324

4. 发明专利

JP5273866B2 Multiplier / accumulator unit 有权
公开(公告)号：JP5273866B2
公开(公告)日：2013-08-28
申请号：JP2009255129
申请日：2009-11-06
申请人：テキサスインスツルメンツインコーポレイテッド
发明人： − ピエレジアカローネジーン , セオドロウフランコイス , ボヤドジィアンアレイン
IPC分类号： G06F7/53 , G06F7/533 , G06F7/499 , G06F7/507 , G06F7/508 , G06F7/52 , G06F7/544 , G06F17/10
CPC分类号： G06F7/5338 , G06F7/49921 , G06F7/49963 , G06F7/49968 , G06F7/5443 , G06F9/30014 , G06F9/3885 , G06F2207/382
摘要： A MAC unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arithmetically combining the reduced partial products with said third operand, a final adder for generating a final sum, and a saturation circuitry for selectively rounding or saturating said final sum is provided. A dual MAC unit is also provided.

5. 发明专利

JP2012248208A Large multiplier for programmable logic device 有权
标题翻译：用于可编程逻辑器件的大型多路复用器
公开(公告)号：JP2012248208A
公开(公告)日：2012-12-13
申请号：JP2012172915
申请日：2012-08-03
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： LANGHAMMER MARTIN , THARMALINGAM KUMARA
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324
摘要： PROBLEM TO BE SOLVED: To provide special processing blocks for a programmable logic device (PLD) with logic for reducing or eliminating dependence on a universal programmable resource of the PLD by facilitating execution of a larger multiplication than the one to be executed in a single block.SOLUTION: A plurality of special processing blocks in a PLD including multipliers, and circuitry for an adder which adds results of the multipliers are constituted as larger multipliers by adding selectable circuitry for shifting the results of the multipliers before addition to the special processing blocks. In one embodiment, this fact allows that all except the final addition are performed in the special processing blocks, and the final addition is performed in programmable logic. In another embodiment, circuitry of additional compression and addition allows that even the final addition is performed in the special processing blocks.
摘要翻译：要解决的问题：为可编程逻辑器件（PLD）提供特殊的处理块，其具有用于通过促进执行比要执行的PLD更大的乘法来减少或消除对PLD的通用可编程资源的依赖性的逻辑单块。解决方案：包括乘法器的PLD中的多个特殊处理块和用于加法乘法器的结果的加法器的电路被构成为较大的乘法器，通过增加用于在乘法器的结果之前移位乘法器的特定处理的可选择电路块。在一个实施例中，这个事实允许在特殊处理块中执行除了最终加法之外的所有其它事件，并且以可编程逻辑执行最后的加法。在另一个实施例中，附加压缩和附加的电路允许即使在特殊处理块中执行最终添加。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP4408727B2 Digital circuit 有权
公开(公告)号：JP4408727B2
公开(公告)日：2010-02-03
申请号：JP2004073589
申请日：2004-03-15
申请人： Necエレクトロニクス株式会社
发明人：常喜佐々木 , 淳一郎南谷
IPC分类号： G06F7/507 , G06F7/53 , G06F7/508 , G06F7/52 , G06F7/523
CPC分类号： G06F7/507 , G06F7/508

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式