专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP5273866B2 Multiplier / accumulator unit 有权
公开(公告)号：JP5273866B2
公开(公告)日：2013-08-28
申请号：JP2009255129
申请日：2009-11-06
申请人：テキサスインスツルメンツインコーポレイテッド
发明人： − ピエレジアカローネジーン , セオドロウフランコイス , ボヤドジィアンアレイン
IPC分类号： G06F7/53 , G06F7/533 , G06F7/499 , G06F7/507 , G06F7/508 , G06F7/52 , G06F7/544 , G06F17/10
CPC分类号： G06F7/5338 , G06F7/49921 , G06F7/49963 , G06F7/49968 , G06F7/5443 , G06F9/30014 , G06F9/3885 , G06F2207/382
摘要： A MAC unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arithmetically combining the reduced partial products with said third operand, a final adder for generating a final sum, and a saturation circuitry for selectively rounding or saturating said final sum is provided. A dual MAC unit is also provided.

2. 发明专利

JP4408727B2 Digital circuit 有权
公开(公告)号：JP4408727B2
公开(公告)日：2010-02-03
申请号：JP2004073589
申请日：2004-03-15
申请人： Necエレクトロニクス株式会社
发明人：常喜佐々木 , 淳一郎南谷
IPC分类号： G06F7/507 , G06F7/53 , G06F7/508 , G06F7/52 , G06F7/523
CPC分类号： G06F7/507 , G06F7/508

3. 发明专利

JP2010009592A Combined adder circuit array and and/or plane 审中-公开
标题翻译：组合式ADR电路阵列和/或平面
公开(公告)号：JP2010009592A
公开(公告)日：2010-01-14
申请号：JP2009134314
申请日：2009-06-03
申请人： Panasonic Corp , パナソニック株式会社
发明人： STANSFIELD ANTHONY
IPC分类号： G06F7/50 , G06F7/503 , G06F7/508 , G06F7/533
CPC分类号： G06F7/53 , H03K19/17708
摘要： PROBLEM TO BE SOLVED: To provide a method which modifies a group of full adder circuits to compute a logic function of a set number of input bits.
SOLUTION: Each full adder circuit has first and second data inputs, a data output, a carry input and a carry output. The full adder circuits are interconnected so as to form a carry chain. The method includes the step of setting the first input of each full adder circuit to the same fixed value, the step of connecting each respective input bit of the set number of input bits to the second input of a respective one of the full adder circuits, and the step of using the output of the carry chain of the array of the full adder circuits as the result of the logic function.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种修改一组全加器电路以计算设定数量的输入位的逻辑功能的方法。解决方案：每个全加器电路具有第一和第二数据输入，数据输出，进位输入和进位输出。全加器电路互连以便形成一个进位链。该方法包括将每个全加器电路的第一输入设置为相同的固定值的步骤，将设定数量的输入比特的每个相应输入比特连接到全加器电路的相应一个的第二输入的步骤，作为逻辑功能的结果，使用全加器电路的阵列的进位链的输出的步骤。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP3748119B2 Multiple-valued logic circuit 失效
公开(公告)号：JP3748119B2
公开(公告)日：2006-02-22
申请号：JP32924795
申请日：1995-12-18
申请人：富士通株式会社
发明人：求 ▲高▼津
IPC分类号： G06F7/50 , G06G7/14 , G06F7/503 , G06F7/508 , H03K19/20

6. 发明专利

JP2005182346A Adding circuit 有权
标题翻译：增加电路
公开(公告)号：JP2005182346A
公开(公告)日：2005-07-07
申请号：JP2003420513
申请日：2003-12-18
申请人： Texas Instr Japan Ltd , 日本テキサス・インスツルメンツ株式会社
发明人： AWAKA KAORU , TAKEGAMA AKIHIRO , TOYONO YUTAKA , MURAMATSU SHIGETOSHI
IPC分类号： G06F7/50 , G06F7/508 , G06F7/52 , G06F7/523 , G06F7/53
CPC分类号： G06F7/506 , G06F7/507
摘要： PROBLEM TO BE SOLVED: To provide an adding circuit for quickly executing addition without increasing power consumption, and a multiplying circuit and a multiplying/adding circuit having the adding circuit in the final stage. SOLUTION: The delay of a signal to be inputted from a Wallace tree to an adding circuit in the final stage is maximized in a middle rank bit range, and made smaller in low rank and high rank bit ranges. In the low order bit range, addition is performed by a carry increment adder 1 of level 1 whose carry propagation to a higher digit is relatively slow, and in the middle rank bit range, addition is performed by the carry increment adder 1 of level 2 whose carry propagation is quicker, and in the high rank bit range, addition is performed by a high speed carry selector adder 3. Thus, the addition is performed by an addition system suited to the delay trend of a signal input timing in each bit range so that the circuit scale and power consumption can be suppressed, and that the arithmetic operation can be quickened. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于在不增加功耗的情况下快速执行加法的加法电路，以及在最后阶段具有加法电路的乘法电路和乘法/加法电路。解决方案：从华莱士树到最后阶段的加法电路输入的信号的延迟在中间位位置范围内最大化，在低位和高位位范围内变小。在低位比特范围内，通过进位增量加法器1执行加法运算，其进位传播到较高数字相对较慢，而在中间位比特范围内，加法由进位增量加法器1执行2级其进位传播更快，并且在高位比特范围内，由高速进位选择器加法器3执行加法。因此，通过适合于每个比特范围中的信号输入定时的延迟趋势的相加系统来执行相加从而可以抑制电路规模和功耗，并且可以加快算术运算。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP3666185B2 The pass transistor logic circuit 失效
公开(公告)号：JP3666185B2
公开(公告)日：2005-06-29
申请号：JP15140397
申请日：1997-06-09
申请人：セイコーエプソン株式会社
发明人：正美橋本
IPC分类号： G06F7/501 , G06F7/50 , G06F7/508 , H03K19/0175 , H03K19/0944

8. 发明专利

JP2004234110A Parity prediction circuit for full adder 有权
公开(公告)号：JP2004234110A
公开(公告)日：2004-08-19
申请号：JP2003019036
申请日：2003-01-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： IKE ATSUSHI
IPC分类号： G06F11/10 , G06F7/38 , G06F7/508
摘要： PROBLEM TO BE SOLVED: To construct a parity prediction circuit of a full adder from a small number of inputs and a small number of elements. SOLUTION: The parity prediction circuit has computing units, each with a first selector which receives the inputs of carry four parity CP [k-1, 0] and CP [k-1, 1] when carry-in Cin=0 and 1 (k is an integer of not more than n) and which outputs either the input CP [k-1, 0] or CP [k-1, 1] as a carry four parity cp [k, 0] according to a generation bit g[k-2] resulting from addition inputs A[k-2] and B[k-2], and a second selector which receives the inputs of the carry four parity CP [k-1, 0] and CP [k-1, 1] and which outputs either the input CP [k-1, 0] or CP [k-1, 1] as an inverted signal of the carry four parity cp [k, 1] according to a propagation bit p [k-2] resulting from the addition inputs A[k-2] and B[k-2]. The computing units are interconnected in a plurality of rows, and either the carry four parity cp [n, 0] or cp [n, 1] is output as a carry four parity CPn according to the carry in Cin at the final selector. COPYRIGHT: (C)2004,JPO&NCIPI

10. 发明专利

JP3370688B2 Adder of the flag generating circuit 失效
公开(公告)号：JP3370688B2
公开(公告)日：2003-01-27
申请号：JP23458191
申请日：1991-09-13
申请人：松下電器産業株式会社
发明人：俊則前田
IPC分类号： G06F7/50 , G06F7/506 , G06F7/508

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式