专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2007207333A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007207333A
公开(公告)日：2007-08-16
申请号：JP2006023875
申请日：2006-01-31
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA , SATOU ATSUYOSHI , SAKUMA MAKOTO , ENDO MASATO , NISHIHARA KIYOHITO , SHUDO KEIJI , IINO HIROHISA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a nonvolatile semiconductor memory which can realize a small threshold distribution range. SOLUTION: This semiconductor integrated circuit device has a memory cell array including a plurality of blocks, and first non-volatile semiconductor memory cells arranged in the memory cell array and having a first charge storage layer, and second non-volatile semiconductor memory cells arranged close to the first non-volatile semiconductor memory cells in the memory cell array and having a charge storage layer. After normally writing data in the first non-volatile semiconductor memory cells, it normally writes data in the second non-volatile semiconductor memory cells. After normally writing data in the second non-volatile semiconductor memory cells, it writes additional data in the first non-volatile semiconductor memory cells. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够实现小的阈值分布范围的非易失性半导体存储器的半导体集成电路器件。解决方案：该半导体集成电路器件具有包括多个块的存储单元阵列和布置在存储单元阵列中并具有第一电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储器布置在存储单元阵列中靠近第一非易失性半导体存储单元并且具有电荷存储层的单元。在第一非易失性半导体存储单元中正常地写入数据之后，通常在第二非易失性半导体存储单元中写入数据。在第二非易失性半导体存储单元中正常地写入数据之后，它将附加数据写入第一非易失性半导体存储单元。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2012174982A Semiconductor memory device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2012174982A
公开(公告)日：2012-09-10
申请号：JP2011037223
申请日：2011-02-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO
IPC分类号： H01L27/115 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L23/522 , H01L29/41 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L21/76229 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device, and a manufacturing method of the semiconductor memory device, both of which can obtain a short margin between an electric contact and an active area.SOLUTION: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a plurality of element isolation insulators which are formed on an upper part of the semiconductor substrate and divide the upper part to a plurality of active areas extending in a first direction; and an electric contact connected to the active areas. A recessed region is formed over the entire active area in a second direction intersecting perpendicularly to the first direction in a part of area of the first direction among a top surface of each of the active areas. Positions of two of the electric contacts respectively connected to adjoining active areas are mutually different in the first direction. The electric contact contacts with a side surface of the recessed region, but does not contact with a bottom surface thereof.
摘要翻译：解决的问题：提供半导体存储器件以及半导体存储器件的制造方法，它们都可以在电接触和有源区之间获得短距离。解决方案：根据实施例的半导体存储器件包括：半导体衬底; 多个元件隔离绝缘体，其形成在所述半导体基板的上部，并将所述上部分割成沿着第一方向延伸的多个有效区域; 以及连接到活动区域的电触点。在每个有源区域的顶表面中，沿第一方向的一部分区域垂直于第一方向相交的第二方向在整个有效区域上形成凹陷区域。分别连接到邻接有效区域的两个电触点的位置在第一方向上是相互不同的。电接触与凹陷区域的侧表面接触，但不与其底表面接触。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012019020A Nonvolatile memory unit 审中-公开
标题翻译：非易失性存储单元
公开(公告)号：JP2012019020A
公开(公告)日：2012-01-26
申请号：JP2010154850
申请日：2010-07-07
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGASHIMA YUKINOBU , AKAHORI HIROSHI , IWAZAWA KAZUAKI , CHANG YONG-GANG , ICHIKAWA HISASHI , KONDO SHIGEO , KONDO MASAKI , NISHIHARA KIYOHITO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883 , H01L27/11521
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory unit having a high voltage endurance between an active region of a substrate and a control gate electrode.SOLUTION: The nonvolatile memory unit has: a substrate having device isolating dielectric trenches; first and second tunnel dielectric films and first and second floating gate electrodes formed on the substrate on both sides of each device isolating trench; an inter-gate dielectric film formed to cover upper surfaces of the first and second floating gate electrodes and to fill at least an upper portion of each device isolating dielectric trench, which is located between the first and second floating gate electrodes and between the first and second tunnel dielectric films; and a control gate electrode formed on the inter-gate dielectric film. The inter-gate dielectric film includes: an electron trap layer made of a first dielectric material having the ability to trap electrons; and first and second dielectric layers made of a second dielectric material smaller than the first material in the ability to trap electrons, and sandwiching the electron trap layer therebetween.
摘要翻译：要解决的问题：提供一种在基板的有源区域和控制栅电极之间具有高耐压性的非易失性存储单元。解决方案：非易失性存储器单元具有：具有器件隔离电介质沟槽的衬底; 第一和第二隧道介电膜以及在每个器件隔离沟槽的两侧上形成在衬底上的第一和第二浮栅; 形成为覆盖第一和第二浮栅的上表面并且填充位于第一和第二浮栅之间以及位于第一和第二浮栅之间的每个器件隔离电介质沟槽的至少上部的栅极间电介质膜第二隧道介电膜; 以及形成在栅极间电介质膜上的控制栅电极。栅极间电介质膜包括：由具有捕获电子的能力的第一电介质材料制成的电子俘获层; 以及由捕获电子的能力小于第一材料的第二电介质材料制成的第一和第二电介质层，并且夹在其间的电子陷阱层。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2013201269A Molecular memory and manufacturing method thereof 审中-公开
标题翻译：分子记忆及其制备方法
公开(公告)号：JP2013201269A
公开(公告)日：2013-10-03
申请号：JP2012068434
申请日：2012-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO
IPC分类号： H01L27/105 , H01L27/28 , H01L45/00 , H01L49/00 , H01L51/05
摘要： PROBLEM TO BE SOLVED: To provide a molecular memory, in which variations in characteristics between memory cells are small, and a manufacturing method thereof.SOLUTION: A molecular memory according to an embodiment includes: first wiring that is made of a first conductive material and extends in a first direction; second wiring that is made of a second conductive material different from the first conductive material and extends in a second direction orthogonal to the first direction; and a resistance change type molecular chain disposed between the first wiring and the second wiring. An area, which opposes a center part in a widthwise direction of the second wiring, of a surface on a second wiring side of the first wiring is positioned closer to the second wiring than an area, which opposes an end part in the widthwise direction of the second wiring, of the surface.
摘要翻译：要解决的问题：提供存储单元之间的特性变化小的分子存储器及其制造方法。根据实施方式的分子存储器包括：由第一导电材料制成的第一布线和沿第一方向延伸; 第二布线，其由与第一导电材料不同的第二导电材料制成并沿与第一方向正交的第二方向延伸; 以及设置在第一布线和第二布线之间的电阻变化型分子链。在第一配线的第二配线侧的表面的与第二配线的宽度方向的中心部分相对的区域位于比第二配线的宽度方向的端部相对的区域更靠近第二配线的区域表面的第二个接线。

5. 发明专利

JP2013197499A Molecular memory 审中-公开
标题翻译：分子记忆
公开(公告)号：JP2013197499A
公开(公告)日：2013-09-30
申请号：JP2012065752
申请日：2012-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO , HAYASHI TETSUYA
IPC分类号： H01L27/28 , C07C323/34 , H01L27/105 , H01L45/00 , H01L49/00 , H01L51/05 , H01L51/30
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable molecular memory.SOLUTION: A molecular memory according to an embodiment comprises: first electrodes; second electrodes; and resistance change type molecular chains arranged between the first electrodes and the second electrodes. The first electrodes each include: a core material made of a first conductive material; and side walls formed on the side faces of the core material and made of a second conductive material which is different from the first conductive material. The second electrodes are each made of a third conductive material which is different from the first conductive material. The resistance change type molecular chains are coupled to the first conductive materials.
摘要翻译：要解决的问题：提供高度可靠的分子记忆。解决方案：根据实施方案的分子存储器包括：第一电极; 第二电极; 以及布置在第一电极和第二电极之间的电阻变化型分子链。第一电极各自包括：由第一导电材料制成的芯材; 以及形成在芯材的侧面上并由与第一导电材料不同的第二导电材料制成的侧壁。第二电极各自由与第一导电材料不同的第三导电材料制成。电阻变化型分子链与第一导电材料耦合。

6. 发明专利

JP2010123890A Nonvolatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2010123890A
公开(公告)日：2010-06-03
申请号：JP2008298533
申请日：2008-11-21
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a NAND type flash memory capable of suppressing deterioration in element characteristics of a memory cell accompanying microfabrication. SOLUTION: A nonvolatile semiconductor memory has a device region 1 defined with a device isolation insulating film 10, a tunnel insulating film 2A provided on a surface of the device region 1 between two diffusion layers, an insulator 4A provided on an upper surface of a floating gate 3A, an inter-electrode insulating film 5A provided on a side surface of the floating gate electrode 3A, a first insulator 4A provided on the upper surface of the floating gate 3A, and a control gate electrode 5A provided on the floating gate electrode 3A with the insulator 4A and inter-electrode insulating film 5 interposed, wherein the film thickness T1 of the insulator 4A is larger than the film thickness T2 of the inter-electrode insulating film 5A, which has a slit on the insulator 4A or on the device isolation insulating film 10. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种NAND型闪存，其能够抑制伴随微细加工的存储单元的元件特性的劣化。解决方案：非易失性半导体存储器具有由器件隔离绝缘膜10限定的器件区域1，设置在两个扩散层之间的器件区域1的表面上的隧道绝缘膜2A，设置在上表面上的绝缘体4A 设置在浮置栅极3A的侧表面上的电极间绝缘膜5A，设置在浮置栅极3A的上表面上的第一绝缘体4A，以及设置在浮置栅3A的上表面上的控制栅电极5A 插入有绝缘体4A和电极间绝缘膜5的栅电极3A，其中绝缘体4A的膜厚T1大于绝缘体4A上具有狭缝的电极间绝缘膜5A的膜厚T2，在器件隔离绝缘膜10上。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010114360A Semiconductor device, and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010114360A
公开(公告)日：2010-05-20
申请号：JP2008287697
申请日：2008-11-10
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/20 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L21/28282 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a semiconductor member made of a single-crystal semiconductor material and has excellent characteristics, and to provide a method of manufacturing the same. SOLUTION: An insulating film 12 is formed on a silicon substrate 11 made of single-crystal silicon, an opening 12a is formed in the insulating film 12, and an amorphous silicon film is formed on the insulating film 12 in contact with the silicon substrate 11 through the opening 12a, and subjected to solid-phase epitaxial growth starting at the silicon substrate 11 as a starting point, and then patterned. Consequently, a seed layer formed of single-crystal silicon is formed at a part of a region deviated from a region right above the opening 12a. An amorphous silicon film is deposited so as to cover the seed layer, and subjected to solid-phase epitaxial growth starting at the seed layer as a starting point to form a single-crystal silicon film. The single-crystal silicon film is patterned to form silicon pillars 33. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括由单晶半导体材料制成的半导体部件并具有优异特性的半导体器件，并提供其制造方法。解决方案：在由单晶硅制成的硅衬底11上形成绝缘膜12，在绝缘膜12中形成开口12a，并且在与绝缘膜12接触的绝缘膜12上形成非晶硅膜硅基板11通过开口12a，并且以硅基板11为起点进行固相外延生长，然后进行图案化。因此，在离开开口12a正上方的区域的一部分区域形成由单晶硅形成的晶种层。沉积非晶硅膜以覆盖种子层，并以种子层为起点进行固相外延生长，形成单晶硅膜。图案化单晶硅膜以形成硅柱33.版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2013021102A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2013021102A
公开(公告)日：2013-01-31
申请号：JP2011152672
申请日：2011-07-11
申请人： Toshiba Corp , 株式会社東芝
发明人： SATO HIROYASU , NISHIHARA KIYOHITO , NAWATA HIDEFUMI , ICHIGE MASAYUKI , OBA RYUJI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11524 , H01L29/42336 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can suppress interference between floating gate electrodes while ensuring coupling between a control gate electrode and the floating gate electrode.SOLUTION: The semiconductor storage device comprises: tunnel films 13 each provided on an active area 12; floating gate electrodes 14 each provided on the tunnel film; an interelectrode insulation film 18 provided on the floating gate electrodes and extending in a second direction intersecting a first direction; a control gate electrode 19; lower side insulation parts 16 provided between the active areas neighboring to each other in the second direction, between the tunnel films neighboring to each other in the second direction and between the floating gate electrodes neighboring to each other in the second direction; and upper side insulation parts 17 each provided between the lower side insulation part and the interelectrode insulation film and each having a top face located above a top face of the floating gate electrode. The lower side insulation part has a gas portion. Relative permittivity of the upper side insulation part is higher than that of the lower side insulation part. Relative permittivity of the interelectrode insulation film is higher than that of the upper side insulation part.
摘要翻译：解决的问题：提供一种能够抑制浮栅之间的干扰同时确保控制栅电极和浮栅电极之间的耦合的半导体存储装置。解决方案：半导体存储装置包括：每个设置在有源区12上的隧道膜13; 每个设置在隧道膜上的浮栅电极14; 设置在所述浮栅上并且沿与第一方向交叉的第二方向延伸的电极间绝缘膜18; 控制栅电极19; 下侧绝缘部16设置在第二方向上彼此相邻的有源区域之间，在第二方向上彼此相邻的隧道膜之间以及在第二方向上彼此相邻的浮栅之间。以及上侧绝缘部17，其分别设置在下侧绝缘部和电极间绝缘膜之间，并且各自具有位于浮置栅电极的上表面上方的顶面。下侧绝缘部具有气体部。上侧绝缘部的相对介电常数高于下侧绝缘部的介电常数。电极间绝缘膜的相对介电常数高于上侧绝缘部分。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2012028419A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012028419A
公开(公告)日：2012-02-09
申请号：JP2010163381
申请日：2010-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： IWAZAWA KAZUAKI , NAGASHIMA YUKINOBU , AKAHORI HIROSHI , NISHIHARA KIYOHITO , KONDO MASAKI , KONDO SHIGEO , ICHIKAWA HISASHI , CHANG YONG-GANG
IPC分类号： H01L21/76 , H01L21/8247 , H01L27/08 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same which can form insulator films inside a microfabricated isolation trench having a high aspect ratio.SOLUTION: The semiconductor device manufacturing method in which side faces in parallel with a channel direction of a plurality of gate electrodes provided on a semiconductor substrate via a gate insulator film are included as partial inner walls of isolation trenches provided between neighboring gate electrodes, comprises the steps of forming protective films covering side faces of the gate electrodes, forming isolation trenches by etching the semiconductor substrate using the gate electrodes with the side faces covered with the protective films as a mask, forming first insulator films by oxidation of surfaces of the isolation trenches to fill the bottom portions of the isolation trenches with the respective first insulator films and forming second insulator films on the first insulator films to fill the upper portions including the side faces of the gate electrodes with the respective second insulator films.
摘要翻译：解决的问题：提供一种半导体器件及其制造方法，该半导体器件及其制造方法可以在具有高纵横比的微加工隔离沟槽内形成绝缘膜。解决方案：包括设置在半导体衬底上的多个栅极的通过栅极绝缘膜设置的与沟道方向平行的半导体器件制造方法包括设置在相邻栅电极之间的隔离沟槽的部分内壁包括以下步骤：形成覆盖栅电极的侧面的保护膜，通过使用覆盖有保护膜的侧面作为掩模的栅电极蚀刻半导体衬底形成隔离沟槽，通过氧化表面形成第一绝缘膜所述隔离沟槽用相应的第一绝缘膜填充所述隔离沟槽的底部，并在所述第一绝缘膜上形成第二绝缘膜，以填充包括所述栅极电极的侧面的上部，并具有相应的第二绝缘膜。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2010138015A Apparatus for manufacturing carbon nanotube, and method for sorting carbon nanotube 审中-公开
标题翻译：用于制造碳纳米管的装置和用于分选碳纳米管的方法
公开(公告)号：JP2010138015A
公开(公告)日：2010-06-24
申请号：JP2008314757
申请日：2008-12-10
申请人： Toshiba Corp , 株式会社東芝
发明人： MIZUKAMI MAKOTO , NISHIHARA KIYOHITO
IPC分类号： C01B31/02 , B82B3/00 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L29/06 , H01L29/78 , H01L29/786 , H01L49/00
CPC分类号： B03C1/08 , B03C1/24 , B03C2201/20 , B03C2201/26 , B82Y30/00 , B82Y40/00 , C01B32/172 , C01B2202/22
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and a method for sorting carbon nanotubes by properties thereof. SOLUTION: The apparatus for sorting carbon nanotubes comprises an introduction section 2 by which a first carbon nanotube SCNT having a first magnetic property and a second carbon nanotube MCNT having a second magnetic property are commonly introduced, first and second recovery sections 4A, 4B to recover the first and second carbon nanotubes SCNT, MCNT, respectively, a transportation section 3 to transport the first and second carbon nanotubes SCNT, MCNT from the introduction section 2 to the recovery section 4A, 4B and a magnetic field generation section 5 to apply a magnetic field H to the carbon nanotubes SCNT, MCNT, wherein an interaction between the first magnetic property and the magnetic field H sorts the first carbon nanotube SCNT and the second carbon nanotube MCNT. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供通过其碳纳米管的特性来分选碳纳米管的装置和方法。解决方案：用于分选碳纳米管的装置包括引入部分2，其中通常引入具有第一磁性的第一碳纳米管SCNT和具有第二磁性的第二碳纳米管MCNT，第一和第二恢复部分4A， 4B分别回收第一和第二碳纳米管SCNT，MCNT，将第一和第二碳纳米管SCNT，MCNT从导入部2输送到回收部4A，4B和磁场产生部5的输送部3，对碳纳米管SCNT，MCNT施加磁场H，其中第一磁性和磁场H之间的相互作用使第一碳纳米管SCNT和第二碳纳米管MCNT排列。版权所有（C）2010，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式