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1. 发明专利

JP2007317874A Non-volatile semiconductor storage device 审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：JP2007317874A
公开(公告)日：2007-12-06
申请号：JP2006145661
申请日：2006-05-25
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： IINO HIROHISA , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device capable of being micronized and laminated. SOLUTION: A NAND (NOT AND) type flash memory is equipped with a first laminate in which a plurality of first gate electrodes included in a plurality of first memory cells are laminated through an insulating layer, a second laminate in which a plurality of second gate electrodes included in a plurality of second memory cells are laminated through the insulating layer, first and second gate insulating films 16, respectively provided on the side surfaces of the first and second laminates while comprising a charge accumulating layer 14 therein, a first semiconductor layer 12 comprising a first pillar provided on the side surface of the first gate insulating film and a second pillar provided on the side surface of the second gate insulating film while being connected electrically to the first pillar, a first selection transistor SST connected in series to the first memory cell while being provided on the first pillar, and a second selection transistor SDT connected in series to the second memory cell while being provided on the second pillar. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够进行微粉化和层压的非易失性半导体存储装置。解决方案：NAND（非AND）型闪速存储器配备有第一层压体，其中包括在多个第一存储单元中的多个第一栅电极通过绝缘层层叠，第二层压体，其中多个包括在多个第二存储单元中的第二栅极电极通过绝缘层层叠，分别设置在第一和第二层压体的侧表面上的第一和第二栅极绝缘膜16，同时包括电荷累积层14，第一栅极绝缘膜半导体层12，包括设置在第一栅极绝缘膜的侧表面上的第一柱和设置在第二栅极绝缘膜的侧表面上并与第一柱电连接的第二柱;串联连接的第一选择晶体管SST; 提供在第一支柱上的第一存储单元，以及与第一支柱串联连接的第二选择晶体管SDT d存储单元，同时被提供在第二柱上。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007207333A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007207333A
公开(公告)日：2007-08-16
申请号：JP2006023875
申请日：2006-01-31
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA , SATOU ATSUYOSHI , SAKUMA MAKOTO , ENDO MASATO , NISHIHARA KIYOHITO , SHUDO KEIJI , IINO HIROHISA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a nonvolatile semiconductor memory which can realize a small threshold distribution range. SOLUTION: This semiconductor integrated circuit device has a memory cell array including a plurality of blocks, and first non-volatile semiconductor memory cells arranged in the memory cell array and having a first charge storage layer, and second non-volatile semiconductor memory cells arranged close to the first non-volatile semiconductor memory cells in the memory cell array and having a charge storage layer. After normally writing data in the first non-volatile semiconductor memory cells, it normally writes data in the second non-volatile semiconductor memory cells. After normally writing data in the second non-volatile semiconductor memory cells, it writes additional data in the first non-volatile semiconductor memory cells. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够实现小的阈值分布范围的非易失性半导体存储器的半导体集成电路器件。解决方案：该半导体集成电路器件具有包括多个块的存储单元阵列和布置在存储单元阵列中并具有第一电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储器布置在存储单元阵列中靠近第一非易失性半导体存储单元并且具有电荷存储层的单元。在第一非易失性半导体存储单元中正常地写入数据之后，通常在第二非易失性半导体存储单元中写入数据。在第二非易失性半导体存储单元中正常地写入数据之后，它将附加数据写入第一非易失性半导体存储单元。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2003037251A Semiconductor device and manufacturing method for the semiconductor device 审中-公开
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：JP2003037251A
公开(公告)日：2003-02-07
申请号：JP2001225027
申请日：2001-07-25
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： ARAI NORIHISA , ARAI FUMITAKA , ARITOME SEIICHI , SHIRATA RIICHIRO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent remaining of unetched parts and overetching, even when simultaneously patterning a high concentration region and a low concentration region.
SOLUTION: After forming an element isolation oxide film 118, a CMP is conducted with a silicon nitride film 118 as a stopper and the element isolation oxide film 118 is planarized. Thereafter, when the silicon nitride film 118 is removed, a step A' is formed between the peak part of the element isolation oxide film 118 and polysilicon films 106 and 113. Then, when the polysilicon film is deposited further on the polysilicon films 106 and 113, 'drift' of the polysilicon film is generated, and the film becomes thick on the side of a memory cell region and the drift is not generated on a peripheral circuit region. In order to offset the difference in the total thickness of the gate electrode film due to that, the film thickness of the polysilicon film 113 in the peripheral circuit region is formed larger than the film thickness of the polysilicon film 106 in the memory cell region by a prescribed amount.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：即使当同时构图高浓度区域和低浓度区域时，为了防止未蚀刻部分的残留和过蚀刻。解决方案：在形成元件隔离氧化膜118之后，用氮化硅膜118作为阻挡层进行CMP，并且元件隔离氧化膜118被平坦化。此后，当去除氮化硅膜118时，在元件隔离氧化膜118的峰部分和多晶硅膜106和113之间形成步骤A'。然后，当多晶硅膜进一步沉积在多晶硅膜106上时如图113所示，产生多晶硅膜的“漂移”，并且膜在存储单元区域侧变厚，并且在外围电路区域上不产生漂移。为了抵消栅极电极膜的总厚度的差异，由于周边电路区域中的多晶硅膜113的膜厚被形成为大于存储单元区域中的多晶硅膜106的膜厚度，规定金额。

4. 发明专利

JP2007207332A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007207332A
公开(公告)日：2007-08-16
申请号：JP2006023864
申请日：2006-01-31
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： IINO HIROHISA , ARAI FUMITAKA
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5646 , G11C2216/14
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a nonvolatile semiconductor memory in which page flag data can be read out at high speed. SOLUTION: A plurality of pages (PAGE) include respectively a user region in which rewriting by a user can be performed and a page flag region 9 in which page flag data indicating the present state of the page is written, a page buffer 3 includes a page buffer part 11 for user holding temporarily user data and a page buffer part 13 for page flag holding temporarily page flag data, the page flag data is recorded in the nonvolatile semiconductor memory cell arranged in the page flag region 9 with binary data, the user data is recorded in the nonvolatile semiconductor memory cell arranged in the user region with multi-level data. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有非易失性半导体存储器的半导体集成电路器件，其中可以高速读出页面标志数据。多个页面（PAGE）分别包括可以执行用户重写的用户区域和写入指示页面当前状态的页面标志数据的页面标记区域9，页面缓冲器 3包括用于持有临时用户数据的用户的页面缓冲器部分11和用于页面标志保持临时页面标志数据的页面缓冲器部分13，页面标志数据被记录在布置在页面标志区域9中的具有二进制数据的非易失性半导体存储器单元，用户数据被记录在具有多级数据的布置在用户区域中的非易失性半导体存储单元中。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2003297944A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003297944A
公开(公告)日：2003-10-17
申请号：JP2002102847
申请日：2002-04-04
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SHIMIZU AKIRA , ARAI NORIHISA , ARAI FUMITAKA
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a high voltage driving system transistor, and a memory cell and a low voltage driving system transistor wherein junction breakdown strength between a source/drain electrode and a substrate does not disperse and short circuit is not generated.
SOLUTION: A first gate oxide film (5) of a high voltage driving system transistor and a second gate oxide film (7) of a memory cell transistor and a low voltage driving system transistor are formed on a silicon substrate (1). The film thickness of the first gate oxide film (5) in a region, wherein a contact plug 14 of a high voltage driving system transistor is formed, and the film thickness of the second gate oxide film (7) in a region, wherein a contact plug 15 of a memory cell transistor and a low voltage driving system transistor is formed, are made equal including the absence of films.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有高电压驱动系统晶体管的半导体器件，以及存储单元和低电压驱动系统晶体管，其中源/漏电极和衬底之间的结击穿强度不分散和短路电路不产生。解决方案：在硅衬底（1）上形成高电压驱动系统晶体管的第一栅极氧化膜（5）和存储单元晶体管和低电压驱动系统晶体管的第二栅氧化膜（7）。在形成高电压驱动系统晶体管的接触插塞14的区域中的第一栅极氧化膜（5）的膜厚以及第二栅极氧化膜（7）的区域的膜厚，其中，形成存储单元晶体管的接触插头15和低电压驱动系统晶体管，使其不含膜。版权所有（C）2004，JPO

6. 发明专利

JP2007157854A Nonvolatile semiconductor memory device, and manufacturing method thereof 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2007157854A
公开(公告)日：2007-06-21
申请号：JP2005348371
申请日：2005-12-01
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： IINO HIROHISA , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To achieve micronization/higher integration/easiness in working of a memory cell transistor by decreasing aspect ratio. SOLUTION: The memory cell transistor comprises a plurality of active regions AA which are separated from each other by an element separation region 30 and extend in column direction, a plurality of word lines WL which are orthogonal to the plurality of active regions and extend in row direction, an SOI semiconductor layer 14 which is arranged at the intersection of the plurality of word lines and the plurality of active regions arranged in an SOI insulating layer 12, a source/drain region 16, a tunnel insulating film 18 arranged on the SOI semiconductor layer, a floating gate polysilicon electrode layer 4 arranged on the tunnel insulating film on the SOI semiconductor layer sandwiched by the source/drain region, an intergate insulating film 25 arranged on the floating gate polysilicon electrode layer, and a control gate metal electrode layer 70 arranged on the floating gate polysilicon electrode layer 4 through the intergate insulating film. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过降低纵横比来实现存储单元晶体管的微粉化/更高的集成/容易性的工作。解决方案：存储单元晶体管包括多个有源区AA，其通过元件分离区域30彼此分离并在列方向上延伸，多个字线WL与多个有源区域正交，在行方向上延伸的SOI半导体层14布置在布置在SOI绝缘层12，源极/漏极区域16和隧道绝缘膜18中的多个字线和多个有源区域的交叉处的交叉处 SOI半导体层，布置在由源极/漏极区夹持的SOI半导体层上的隧道绝缘膜上的浮栅多晶硅电极层4，布置在浮栅多晶硅电极层上的栅间绝缘膜25和控制栅极金属布置在浮栅多晶硅电极层4上的电极层70。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006073939A Nonvolatile semiconductor memory and manufacturing method thereof 审中-公开
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：JP2006073939A
公开(公告)日：2006-03-16
申请号：JP2004258523
申请日：2004-09-06
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： IINO HIROHISA , ARAI FUMITAKA , MATSUNAGA YASUHIKO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/0483 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11551 , H01L27/1203 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory which can reduce short channel effect of a memory cell transistor.
SOLUTION: The non-volatile semiconductor memory comprises an insulating layer 1 and a plurality of memory cell transistors disposed in a matrix on the insulating layer 1. A memory cell transistor M
11 is a depletion type MIS transistor having opposing first conductivity type (n
+ -type) source and drain regions 421, 422 disposed on the insulating layer 1, the channel region 411 of a first conductivity type (n-type) which is held between source and drain regions 421, 422 with impurity density lower than that of the source and drain regions 421, 422, a floating gate electrode 13 isolated and disposed on the channel region 411, and a control gate electrode 15 isolated and disposed on the floating gate electrode 13.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以减少存储单元晶体管的短沟道效应的非易失性半导体存储器。解决方案：非易失性半导体存储器包括绝缘层1和布置在绝缘层1上的矩阵中的多个存储单元晶体管。存储单元晶体管SB 11是耗尽型 MIS晶体管具有相对的第一导电类型（n

8. 发明专利

JP2015053098A 不揮発性半導体記憶装置审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2015053098A
公开(公告)日：2015-03-19
申请号：JP2013186605
申请日：2013-09-09
申请人：株式会社東芝 , Toshiba Corp
发明人： FUNATSUKI RIEKO , FUTAYAMA TAKUYA , ARAI FUMITAKA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3431 , G11C16/3459
摘要：【課題】書き込み時間を短縮させた不揮発性半導体記憶装置を提供する。【解決手段】不揮発性半導体記憶装置は、メモリセルアレイと、制御回路とを備える。前記メモリセルアレイは、複数のしきい値を設定することで多値を記録可能な不揮発性のメモリセルが配列されて構成される。前記制御回路は、消去状態にある前記メモリセルのしきい値レベルを判定する事前ベリファイ動作と、前記事前ベリファイ動作の判定結果に基づき複数の書き込み電圧の中から1つの書き込み電圧を選択して前記メモリセルへの書き込みを行う書き込み動作と、を実行する。【選択図】図5
摘要翻译：要解决的问题：提供能够减少写入时间的非易失性半导体存储装置。解决方案：非易失性半导体存储装置包括：存储单元阵列; 和控制电路。存储单元阵列被配置为使得可以通过设置多个阈值来记录多级数据的非易失性存储单元被排列成阵列。控制电路执行用于确定擦除状态下的存储单元的阈值电平的预验证操作，以及用于根据预处理的确定结果从多个写入电压中选择一个写入电压的写入操作，验证对存储单元的操作和写入数据。

9. 发明专利

JP2013201215A Nonvolatile semiconductor memory device and method for manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2013201215A
公开(公告)日：2013-10-03
申请号：JP2012067723
申请日：2012-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKAGUCHI TAKESHI , ARAI FUMITAKA
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of diffusing an impurity of a desired concentration into a desired region with good controllability.SOLUTION: According to an embodiment, there is provided a nonvolatile semiconductor memory device in which a memory cell array layer CA11 in which a memory cell is formed on a semiconductor layer 11 serving as an active region and a memory cell array layer CA12 in which a memory cell is formed on a semiconductor layer 21 serving as the active region are laminated. The semiconductor layer 11 is disposed on a diffusion source layer 101 including an impurity atom which imparts conductivity to the semiconductor layer 11 via an insulating film 102. The semiconductor layer 21 is disposed on one principal surface of a diffusion source layer 112 including an impurity atom via an insulating film 111.
摘要翻译：要解决的问题：提供一种能够将期望浓度的杂质扩散到具有良好可控性的期望区域的非易失性半导体存储器件。解决方案：根据实施例，提供了一种非易失性半导体存储器件，其中存储单元阵列在用作有源区的半导体层11上形成存储单元的层CA11和在作为有源区的半导体层21上形成有存储单元的存储单元阵列层CA12。半导体层11设置在包括通过绝缘膜102赋予半导体层11的导电性的杂质原子的扩散源层101.半导体层21设置在包括杂质原子的扩散源层112的一个主表面上经由绝缘膜111。

10. 发明专利

JP2011065687A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011065687A
公开(公告)日：2011-03-31
申请号：JP2009213140
申请日：2009-09-15
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKEKIDA HIDEHITO , ARAI FUMITAKA
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To respond to variation in initial write voltage caused by variation in manufacturing processes. SOLUTION: Within a flash memory device, a ROM fuse is provided and a trimming process is performed for each word line. The sum of n added voltages ΔVpgm required for a primary write voltage Vpgm is previously stored within the ROM fuse as the primary write voltage Vpgm. In a writing process, the primary write voltage Vpgm of a corresponding word line is read from the ROM fuse and set. COPYRIGHT: (C)2011,JPO&INPIT

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