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1. 发明专利

JP2006073939A Nonvolatile semiconductor memory and manufacturing method thereof 审中-公开
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：JP2006073939A
公开(公告)日：2006-03-16
申请号：JP2004258523
申请日：2004-09-06
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： IINO HIROHISA , ARAI FUMITAKA , MATSUNAGA YASUHIKO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/0483 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11551 , H01L27/1203 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory which can reduce short channel effect of a memory cell transistor.
SOLUTION: The non-volatile semiconductor memory comprises an insulating layer 1 and a plurality of memory cell transistors disposed in a matrix on the insulating layer 1. A memory cell transistor M
11 is a depletion type MIS transistor having opposing first conductivity type (n
+ -type) source and drain regions 421, 422 disposed on the insulating layer 1, the channel region 411 of a first conductivity type (n-type) which is held between source and drain regions 421, 422 with impurity density lower than that of the source and drain regions 421, 422, a floating gate electrode 13 isolated and disposed on the channel region 411, and a control gate electrode 15 isolated and disposed on the floating gate electrode 13.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以减少存储单元晶体管的短沟道效应的非易失性半导体存储器。解决方案：非易失性半导体存储器包括绝缘层1和布置在绝缘层1上的矩阵中的多个存储单元晶体管。存储单元晶体管SB 11是耗尽型 MIS晶体管具有相对的第一导电类型（n

2. 发明专利

JP2007207333A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007207333A
公开(公告)日：2007-08-16
申请号：JP2006023875
申请日：2006-01-31
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA , SATOU ATSUYOSHI , SAKUMA MAKOTO , ENDO MASATO , NISHIHARA KIYOHITO , SHUDO KEIJI , IINO HIROHISA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a nonvolatile semiconductor memory which can realize a small threshold distribution range. SOLUTION: This semiconductor integrated circuit device has a memory cell array including a plurality of blocks, and first non-volatile semiconductor memory cells arranged in the memory cell array and having a first charge storage layer, and second non-volatile semiconductor memory cells arranged close to the first non-volatile semiconductor memory cells in the memory cell array and having a charge storage layer. After normally writing data in the first non-volatile semiconductor memory cells, it normally writes data in the second non-volatile semiconductor memory cells. After normally writing data in the second non-volatile semiconductor memory cells, it writes additional data in the first non-volatile semiconductor memory cells. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够实现小的阈值分布范围的非易失性半导体存储器的半导体集成电路器件。解决方案：该半导体集成电路器件具有包括多个块的存储单元阵列和布置在存储单元阵列中并具有第一电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储器布置在存储单元阵列中靠近第一非易失性半导体存储单元并且具有电荷存储层的单元。在第一非易失性半导体存储单元中正常地写入数据之后，通常在第二非易失性半导体存储单元中写入数据。在第二非易失性半导体存储单元中正常地写入数据之后，它将附加数据写入第一非易失性半导体存储单元。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2011014182A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011014182A
公开(公告)日：2011-01-20
申请号：JP2009155472
申请日：2009-06-30
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA YASUHIKO
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To improve a write-in property of a MONOS type nonvolatile memory cell.SOLUTION: The nonvolatile semiconductor memory device includes an element separation insulating film ST1 extended to a first direction and separating a semiconductor substrate 1 into a plurality of element regions, a plurality of word lines extended to a second direction crossing to a first direction, a memory cell string including a plurality of memory cells connected on the element regions, a bit line contact connected to one end of the memory cell string through a selection gate transistor, and a source line contact connected to the other end of the memory cell string through the selection gate transistor; a memory cell 4 has a tunnel insulating film 41 formed on the semiconductor substrate 1, a charge storing layer 42 formed on the tunnel insulating film 41 and including an insulating film, and gate electrode 44 formed on the charge storing layer 42 and connected to the word line, wherein large auxiliary voltage being larger than pass voltage is applied to a first adjacent word line out of first and second adjacent word lines adjacent to a selection word line during write-in.
摘要翻译：要解决的问题：提高MONOS型非易失性存储单元的写入特性。解决方案：非易失性半导体存储器件包括延伸到第一方向的元件隔离绝缘膜ST1，并将半导体衬底1分离成多个元件区域，延伸到与第一方向交叉的第二方向的多个字线，包括连接在元件区域上的多个存储单元的存储单元串，通过选择连接到存储单元串的一端的位线触点栅极晶体管和通过选择栅极晶体管连接到存储单元串的另一端的源极线接触; 存储单元4具有形成在半导体衬底1上的隧道绝缘膜41，形成在隧道绝缘膜41上并包括绝缘膜的电荷存储层42，以及形成在电荷存储层42上并连接到电荷存储层42上的栅电极44。字线，其中在写入期间，与选择字线相邻的第一和第二相邻字线中的第一相邻字线大于通过电压的大的辅助电压。

4. 发明专利

JP2006310454A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006310454A
公开(公告)日：2006-11-09
申请号：JP2005129540
申请日：2005-04-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KUTSUKAKE HIROYUKI , MATSUNAGA YASUHIKO , MIYAZAKI SHOICHI
IPC分类号： H01L21/8247 , H01L21/768 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L23/485 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which wiring layers that should not be connected are not connected each other. SOLUTION: A semiconductor memory device comprises a semiconductor substrate 1 having a first surface. Two first gate transistors ST are provided on the first surface in the first direction. A source/drain region 7 sandwiches a channel region. A first interlayer insulating film 13 fills the first intergate region between two first gate transistors, and has an upper surface which is lower than the upper surfaces of the two first gate transistors. A second interlayer insulating film 15 is provided on the two first gate transistors and the first interlayer insulating film. Two wiring layers 16 are provided in the second interlayer insulating film to extend in the direction across the first direction electrically insulated from each other. A contact plug 17 is provided in the first interlayer insulating film and the second interlayer insulating film, and contacts the wiring layer and source/drain region. The second interlayer insulating film fills between the two wiring layers. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其中不应该连接的布线层不相互连接。解决方案：半导体存储器件包括具有第一表面的半导体衬底1。两个第一栅极晶体管ST沿第一方向设置在第一表面上。源极/漏极区域7夹着沟道区域。第一层间绝缘膜13填充两个第一栅极晶体管之间的第一栅极间区域，并且具有比两个第一栅极晶体管的上表面低的上表面。第二层间绝缘膜15设置在两个第一栅极晶体管和第一层间绝缘膜上。在第二层间绝缘膜中设置两个布线层16，以在彼此电绝缘的第一方向上延伸。接触插塞17设置在第一层间绝缘膜和第二层间绝缘膜中，并与布线层和源/漏区接触。第二层间绝缘膜填充在两个布线层之间。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005101066A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2005101066A
公开(公告)日：2005-04-14
申请号：JP2003329996
申请日：2003-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKUMA MAKOTO , ARAI FUMITAKA , MATSUNAGA YASUHIKO
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42324 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein a write voltage cannot be easily reduced and speed cannot be easily increased because of large capacity in a nonvolatile semiconductor storage device. SOLUTION: A floating gate 13 and a control gate 16 are periodically and alternately arranged in the first direction via a gate insulating film 12 on a substrate 11. The floating gate comprises a first portion 13a having a rectangular section; and a second portion 13b that is positioned nearly at the center of the first portion, has a rectangular section, and has length in a direction in parallel with a first direction that is shorter than the first portion. The control gate comprises a third portion 16a between the second portions of a pair of adjacent floating gates, and a fourth portion 16b positioned between the first portions of the pair of adjacent floating gates. One memory cell is composed of the floating gate and a pair of control gates positioned at both the sides, adjacent memory cells share the control gate positioned between the adjacent memory cells, and the floating gate is driven by the capacitive coupling between the floating gate and the pair of control gates at both the sides. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题为了解决由于非易失性半导体存储装置中的大容量而不能容易地减小写入电压并且不能容易地增加速度的问题。解决方案：浮置栅极13和控制栅极16经由衬底11上的栅极绝缘膜12沿第一方向周期性地交替布置。浮动栅极包括具有矩形截面的第一部分13a; 并且位于第一部分的中心附近的第二部分13b具有矩形截面，并且在与第一部分短的第一方向上具有平行的方向上的长度。控制门包括在一对相邻浮动栅极的第二部分之间的第三部分16a和位于一对相邻浮动栅极的第一部分之间的第四部分16b。一个存储单元由浮置栅极和位于两侧的一对控制栅极组成，相邻的存储单元共享位于相邻存储单元之间的控制栅极，并且浮置栅极由浮动栅极与浮置栅极之间的电容耦合驱动两侧的一对控制门。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2004186252A Nonvolatile semiconductor memory device and its manufacturing method 有权
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2004186252A
公开(公告)日：2004-07-02
申请号：JP2002348933
申请日：2002-11-29
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIRATA RIICHIRO , YAEGASHI TOSHITAKE , SHIMIZU AKIRA , MATSUNAGA YASUHIKO , ICHIGE MASAYUKI , MEGURO TOSHITAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To realize the construction of a cell made fine and the lowering of write electric potential.
SOLUTION: A device isolation insulating layer 16 has an STI structure with its upper surface being flat. A floating gate electrode 13 is disposed in a recessed part formed with protruded parts of the device isolating insulating layer 16. Two opposite side surfaces of the floating gate electrode 13 are covered with the device isolation insulating layer 16. The upper surface of the floating gate electrode 13 and the upper surface of the device isolation insulating layer 16 are substantially coincident with each other. An inter-gate insulating layer 17 is formed on the floating gate electrode 13 and the device isolation insulating layer 16. A base of the inter-gate insulating layer 17 is flat. A control gate electrode 18 is disposed on the inter-gate insulating layer 17.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：实现电池的制造精细和写入电位的降低。解决方案：器件隔离绝缘层16具有其上表面平坦的STI结构。浮置栅电极13设置在形成有器件隔离绝缘层16的突出部分的凹部中。浮置栅电极13的两个相对的侧表面被器件隔离绝缘层16覆盖。浮动栅极的上表面电极13和器件隔离绝缘层16的上表面基本上彼此重合。栅极间绝缘层17形成在浮栅电极13和器件隔离绝缘层16上。栅间绝缘层17的基底是平坦的。控制栅电极18设置在栅间绝缘层17上。版权所有（C）2004，JPO＆NCIPI

7. 发明专利

JP2008294220A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008294220A
公开(公告)日：2008-12-04
申请号：JP2007138127
申请日：2007-05-24
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , TAKEUCHI YUJI , SHIGEOKA TAKASHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a technology for suppressing shorting between control gate lines.
SOLUTION: The semiconductor memory device comprises a semiconductor substrate 1 consisting of a memory cell array region 100 and a leading wiring region 150 adjoined to the memory cell array region 100, a memory cell MC provided to the memory cell array region 100, a contact plug CP provided to the leading wiring region 150, and a control gate line CGL which is provided from within the leading wiring region 150 down to within the memory cell array region 100, for connecting the contact plug CP to the memory cell MC. The control line CGL provided in the memory cell array region 100 contains a metal silicide 6A. The control gate line CGL provided in the leading wiring region contains no metal silicide at any one part within the leading wiring region.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于抑制控制栅极线之间短路的技术。解决方案：半导体存储器件包括由存储单元阵列区域100和与存储单元阵列区域100相邻的引线布线区域150构成的半导体衬底1，设置到存储单元阵列区域100的存储单元MC，提供给引线布线区域150的接触塞CP，以及从引导布线区域150内向下设置到存储单元阵列区域100内的控制栅线CGL，用于将接触插塞CP连接到存储单元MC。设置在存储单元阵列区域100中的控制线CGL包含金属硅化物6A。在引导布线区域内设置的控制栅极线CGL在引线布线区域内的任何一个部分都不含有金属硅化物。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2007317923A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007317923A
公开(公告)日：2007-12-06
申请号：JP2006146519
申请日：2006-05-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA YASUHIKO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce an occupied area of a selective gate transistor.
SOLUTION: A nonvolatile semiconductor memory device comprises a semiconductor substrate 11, a memory cell string provided on the semiconductor substrate 11 and constituted of a plurality of memory cells for storing data in accordance with a quantity of the electric charge of a charge storage layer connected in series, a selective gate transistor SDT connected to the end of the memory cell string in series, and a bit line BL formed over the semiconductor susbtrate 11 and connected to the selective gate transistor SDT. The channel region of the selective gate transistor SDT is formed between the semiconductor substrate 11 and the bit line BL.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：减少选择栅极晶体管的占用面积。解决方案：非易失性半导体存储器件包括半导体衬底11，设置在半导体衬底11上并由多个存储单元构成的存储单元串，用于根据电荷存储器的电荷量存储数据串联连接到存储单元串的端部的选择栅极晶体管SDT，以及形成在半导体晶体管11上并连接到选择栅晶体管SDT的位线BL。选择栅极晶体管SDT的沟道区域形成在半导体衬底11和位线BL之间。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006049728A Semiconductor memory and its manufacturing method 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：JP2006049728A
公开(公告)日：2006-02-16
申请号：JP2004231578
申请日：2004-08-06
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L21/768 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/0491 , H01L21/7682 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To avoid the generation of a void in a formation prospective region of linearly arranged bit line contacts CB. SOLUTION: A semiconductor memory is loaded on a semiconductor chip 100; and has bit lines BL, source lines SL, and word lines WL that are perpendicular to the bit lines BL. The memory comprises: bit line side selector gate lines SGD and source line side selector gate lines SGS which are adjacent to both ends of the word line WL arranged in the bit line BL direction, and are arranged in parallel with the word line WL; a memory cell transistor MT arranged at the intersection of the bit line BL and the word line WL, and a selector gate transistor ST arranged at the intersection of the bit line BL and the selector gate line SGD; the bit line contacts CB arranged in the word line direction between the bit line side selector gate lines SGD; and a source line contact CS arranged in the word line direction between the source line side selector gates SGS, wherein an interval L1 between the bit line side selector gate lines SGD is larger than an interval L2 between the source line side selector gate lines SGS. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了避免在线性排列的位线触点CB的形成前景区域中产生空隙。解决方案：半导体存储器装载在半导体芯片100上; 并且具有垂直于位线BL的位线BL，源极线SL和字线WL。该存储器包括：与位线BL方向排列的字线WL的两端相邻的位线侧选择栅极线SGD和源极侧选择栅极线SGS，与字线WL并联布置; 布置在位线BL和字线WL的交点处的存储单元晶体管MT以及布置在位线BL和选择栅极线SGD的交点处的选择栅晶体管ST; 布置在位线侧选择栅极线SGD之间的字线方向上的位线接点CB; 以及在源极侧选择栅SGS之间的字线方向上布置的源极线接触CS，其中位线侧选择栅极线SGD之间的间隔L1大于源极侧选择栅极线SGS之间的间隔L2。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005268619A Nonvolatile semiconductor memory device and its manufacturing method 有权
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2005268619A
公开(公告)日：2005-09-29
申请号：JP2004080809
申请日：2004-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： H01L21/76 , G11C16/04 , H01L21/28 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/94
CPC分类号： G11C16/0433 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device with an improved operational reliability, and also to provide a method for manufacturing the nonvolatile semiconductor device. SOLUTION: This nonvolatile semiconductor memory is provided with a first MOS transistor and a second MOS transistor. The first MOS transistor is formed on a first device area enclosed by a first device separation area via a first gate insulting film and has a gate width direction edge on the above first device separation area. The second MOS transistor is provided with the second gate electrode which is formed on a secondary device area enclosed by a secondary device separation area via a second gate insulating film whose thickness is double the film thickness of the above first gate insulating film and has a gate width direction edge on the above second device separation area. In addition, the width from the contact position of the above first device separation area and the above first gate insulating film to the edge of the top of the above first element separation area is equal to that from the contact position of the above second device separation area and the above second gate insulating film to the edge of the top of the above second device separation area. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有改进的操作可靠性的非易失性半导体存储器件，并且还提供一种用于制造非易失性半导体器件的方法。解决方案：该非易失性半导体存储器设置有第一MOS晶体管和第二MOS晶体管。第一MOS晶体管形成在由第一器件分离区域经由第一栅极绝缘膜包围的第一器件区域上，并且在上述第一器件分离区域上具有栅极宽度方向边缘。第二MOS晶体管设置有第二栅电极，该第二栅电极形成在由次级器件分离区域包围的次级器件区域上，第二栅极绝缘膜的厚度是上述第一栅极绝缘膜的膜厚度的两倍，并具有栅极宽度方向边缘在上述第二设备分离区域上。此外，从上述第一器件分离区域和上述第一栅极绝缘膜的接触位置到上述第一元件分离区域的顶部的边缘的宽度等于从上述第二器件分离的接触位置的宽度区域和上述第二栅极绝缘膜到上述第二器件分离区域的顶部的边缘。版权所有（C）2005，JPO＆NCIPI

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