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1. 发明专利

JP2007207333A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007207333A
公开(公告)日：2007-08-16
申请号：JP2006023875
申请日：2006-01-31
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA , SATOU ATSUYOSHI , SAKUMA MAKOTO , ENDO MASATO , NISHIHARA KIYOHITO , SHUDO KEIJI , IINO HIROHISA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a nonvolatile semiconductor memory which can realize a small threshold distribution range. SOLUTION: This semiconductor integrated circuit device has a memory cell array including a plurality of blocks, and first non-volatile semiconductor memory cells arranged in the memory cell array and having a first charge storage layer, and second non-volatile semiconductor memory cells arranged close to the first non-volatile semiconductor memory cells in the memory cell array and having a charge storage layer. After normally writing data in the first non-volatile semiconductor memory cells, it normally writes data in the second non-volatile semiconductor memory cells. After normally writing data in the second non-volatile semiconductor memory cells, it writes additional data in the first non-volatile semiconductor memory cells. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够实现小的阈值分布范围的非易失性半导体存储器的半导体集成电路器件。解决方案：该半导体集成电路器件具有包括多个块的存储单元阵列和布置在存储单元阵列中并具有第一电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储器布置在存储单元阵列中靠近第一非易失性半导体存储单元并且具有电荷存储层的单元。在第一非易失性半导体存储单元中正常地写入数据之后，通常在第二非易失性半导体存储单元中写入数据。在第二非易失性半导体存储单元中正常地写入数据之后，它将附加数据写入第一非易失性半导体存储单元。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007096358A Method of manufacturing semiconductor storage 有权
标题翻译：制造半导体存储的方法
公开(公告)号：JP2007096358A
公开(公告)日：2007-04-12
申请号：JP2007003749
申请日：2007-01-11
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAKA MASAYUKI , SATOU ATSUYOSHI , YAMASHITA HIROKI , MIZUSHIMA ICHIRO , OZAWA YOSHIO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor storage minimized in the interference between adjacent cells even if advancing fining and shortening the distance between cells.
SOLUTION: The method includes processes of: achieving a structure, where a cell section gate insulating film 2 and a first conductive layer 3 are laminated on the surface of a semiconductor substrate 1 successively so that the upper end face of the first conductive layer 3 becomes lower than that of an element separation insulating film 7; arranging a conductive interlayer insulating film 8a comprising an insulating film whose relative dielectric constant is larger than that of a silicon oxide film on the top section of the first conductive layer 3 while the conductive interlayer insulating film 8a is separated by an element separation insulating film 7 mutually; and arranging a second conductive layer 10 on the conductive interlayer insulating film 8a of each memory cell column while the bottom surface of the second conductive layer 10 is in contact with the upper end face of the element separation insulating film 7 so that wiring becomes common to the memory cell column.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种在相邻单元之间的干扰中使半导体存储器制造最小化的方法，即使推进精细化和缩短单元之间的距离。解决方案：该方法包括以下处理：实现在半导体衬底1的表面上依次层叠单元部分栅极绝缘膜2和第一导电层3的结构，使得第一导电层3变得低于元件分离绝缘膜7的层3; 布置导电层间绝缘膜8a，其中导电层间绝缘膜8a由元件隔离绝缘膜7分开，该绝缘膜的相对介电常数大于第一导电层3的顶部上的氧化硅膜的介电常数相互; 并且在第二导电层10的底表面与元件隔离绝缘膜7的上端面接触的同时，在每个存储单元列的导电层间绝缘膜8a上布置第二导电层10，使得布线变得普遍存储单元列。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2005100501A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2005100501A
公开(公告)日：2005-04-14
申请号：JP2003330386
申请日：2003-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SATOU ATSUYOSHI , MATSUNAGA YASUHIKO , ARAI FUMITAKA
IPC分类号： G11C16/06 , G11C11/34 , G11C16/04 , G11C16/12 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： PROBLEM TO BE SOLVED: To provide an efficient writing/reading/erasing operation system in a nonvolatile semiconductor memory having a side wall control type memory cell structure. SOLUTION: The nonvolatile semiconductor memory is constructed in such a manner that memory cell transistors each having a side wall control gate structure capable of electrically writing/erasing data are serially connected in a column direction, memory cell units whose one end of each is connected to a bit line through a first selected gate transistor and whose other end is connected to a source line through a second selected gate transistor are arranged in a matrix, memory cell transistors arrayed in the same row is comprised of a memory cell array connected to common first and second control gate lines, and the same high-voltage pulse is applied to two adjacent control gate lines in the memory cell array to perform writing/reading, and block erasure or page erasure is carried out at the time of erasure. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在具有侧壁控制型存储单元结构的非易失性半导体存储器中提供有效的写/读/擦除操作系统。解决方案：非易失性半导体存储器被构造成使得具有能够电写入/擦除数据的侧壁控制栅极结构的存储单元晶体管在列方向上串联连接，存储单元单元的一端通过第一选择的栅极晶体管连接到位线，并且其另一端通过第二选择的栅极晶体管连接到源极线被布置成矩阵，排列在同一行中的存储单元晶体管包括连接的存储器单元阵列到共同的第一和第二控制栅极线，并且将相同的高压脉冲施加到存储单元阵列中的两个相邻的控制栅极线以执行写入/读取，并且在擦除时执行块擦除或页面擦除。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2008078674A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2008078674A
公开(公告)日：2008-04-03
申请号：JP2007269479
申请日：2007-10-16
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIRATA RIICHIRO , ICHIGE MASAYUKI , SATOU ATSUYOSHI , SUGIMAE KIKUKO , HAZAMA HIROAKI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing the capacity between a resistive element and a substrate in a peripheral circuit of a semiconductor device, especially a non-volatile semiconductor memory, such as a flash memory.
SOLUTION: A flash memory is formed in a semiconductor substrate 1, and an element isolation insulating film 2 dividing an element region, a gate oxide film 4 in an element region 3 isolated from the element isolating region 2, a first gate electrode 5 functioning as a floating gate (FG), a second gate electrode material 7 functioning as a control gate (CG: word line) of a central transistor are formed on a first insulating film 6. In the peripheral circuit section, a resistive element 7a is provided comprising the second gate electrode material via the first insulating film 6 on the element isolation insulating film 2. The impurity concentration of the semiconductor substrate 1 below the resistive element 7a is equal to or lower than that of bulk.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够降低半导体器件的外围电路中的电阻元件和衬底之间的电容的半导体存储器件，特别是诸如闪存的非易失性半导体存储器。解决方案：在半导体衬底1中形成闪存，并且将元件区域分隔开的元件隔离绝缘膜2，与元件隔离区域2隔离的元件区域3中的栅氧化膜4，第一栅电极在第一绝缘膜6上形成用作浮栅（FG）的第五绝缘膜（6），在第一绝缘膜6上形成用作中心晶体管的控制栅极（CG：字线）的第二栅电极材料7.在外围电路部分中，通过元件隔离绝缘膜2上的第一绝缘膜6提供包括第二栅电极材料。电阻元件7a下方的半导体衬底1的杂质浓度等于或低于体积。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2008066593A Nonvolatile semiconductor memory and its manufacturing method 审中-公开
标题翻译：非线性半导体存储器及其制造方法
公开(公告)号：JP2008066593A
公开(公告)日：2008-03-21
申请号：JP2006244557
申请日：2006-09-08
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SATOU ATSUYOSHI
IPC分类号： H01L21/8247 , H01L21/822 , H01L27/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To form an optimized resistive element on a semiconductor substrate, and to reduce a chip size.
SOLUTION: This nonvolatile semiconductor memory comprises a resistive element and a memory cell transistor formed on a semiconductor substrate 1. The memory cell transistor comprises a floating gate electrode 3 of a first conductive material, an inter-gate insulating film 8A formed on the floating gate electrode 3, and a control gate electrode 9A formed on the inter-gate insulating film 8A. The resistive element comprises an element separation insulating layer 5 having a recess X, and a resistor 7A of a second conductive material that fills the recess X. The impurity concentration of the second conductive material is lower than that of the first conductive material.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在半导体衬底上形成优化的电阻元件，并减小芯片尺寸。解决方案：该非易失性半导体存储器包括形成在半导体衬底1上的电阻元件和存储单元晶体管。存储单元晶体管包括第一导电材料的浮栅电极3，栅间绝缘膜8A 浮栅电极3和形成在栅间绝缘膜8A上的控制栅电极9A。电阻元件包括具有凹部X的元件隔离绝缘层5和填充凹部X的第二导电材料的电阻器7A。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007165856A Non-volatile semiconductor storage device 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：JP2007165856A
公开(公告)日：2007-06-28
申请号：JP2006288876
申请日：2006-10-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIMAE KIKUKO , ICHIGE MASAYUKI , ARAI FUMITAKA , MATSUNAGA YASUHIKO , SATOU ATSUYOSHI
IPC分类号： H01L21/8247 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device capable of simultaneously obtaining the high integration, high withstand voltage, high speed and easy processing. SOLUTION: This non-volatile semiconductor storage device comprises: a memory cell transistor comprising a floating gate electrode layer on a tunnel insulating film, an inter-gate insulating film, first and second control gate electrode layers and a metal silicide film; a high-voltage transistor comprising a gate electrode layer 51 for high voltage on a gate insulating film 21 for high voltage, an inter-gate insulating film 25 partially opened, first and second control gate electrode layers 48 and 46 and a metal silicide film 53; a low-voltage transistor comprising a floating gate electrode layer 50 on a tunnel insulating film 20, the inter-gate insulating film 25 partially opened, the first and second control gate electrode layers 48 and 46 and the metal silicide film 53; and a liner insulating film 27 directly arranged on a source/drain region of the memory cell transistor, the high-voltage transistor and the low-voltage transistor. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供能够同时获得高集成度，高耐压，高速度和容易处理的非易失性半导体存储装置。解决方案：该非易失性半导体存储器件包括：存储单元晶体管，其包括在隧道绝缘膜上的浮置栅电极层，栅极间绝缘膜，第一和第二控制栅极电极层和金属硅化物膜; 高电压晶体管，包括用于高电压的栅极绝缘膜21上的用于高电压的栅极电极层51，部分开口的栅极间绝缘膜25，第一和第二控制栅极电极层48和46以及金属硅化物膜53 ; 在隧道绝缘膜20上形成浮置栅电极层50，栅极间绝缘膜25部分开放的第一和第二控制栅电极层48,46和金属硅化物膜53的低电压晶体管; 以及直接配置在存储单元晶体管的源极/漏极区域，高压晶体管和低压晶体管上的衬垫绝缘膜27。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2005259898A Nonvolatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2005259898A
公开(公告)日：2005-09-22
申请号：JP2004067712
申请日：2004-03-10
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKUMA MAKOTO , SATOU ATSUYOSHI
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To simplify the connection formation of a floating gate and a control gate of a selection gate transistor.
SOLUTION: This nonvolatile semiconductor memory is provided with a plurality of memory cell transistors Q
cn , Q
c(n-1) , Q
c(n-2) and so on having a first floating gate 81, a first control gate 121 and a first inter-gate insulating film 71 arranged between the first floating gate and the first control gate; an element separation region 28 arranged at a fixed pitch in a word line WL direction with a stripe-shaped pattern in the bit line BL direction; and a selection transistor arranged at the end of the array of the plurality of memory cell transistors, and equipped with a second floating gate 82, a second control gate 122, a second inter-layer insulating film 72 arranged between the second floating gate and the second control gate, and a side wall gate 6 connecting the second floating gate to the second control gate.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了简化选择栅晶体管的浮栅和控制栅的连接形成。解决方案：该非易失性半导体存储器设置有多个存储单元晶体管Q（c-1），（c），（c），c（n-1） -2）等具有第一浮动栅极81，第一控制栅极121和布置在第一浮动栅极和第一控制栅极之间的第一栅极间绝缘膜71; 在字线WL方向以固定间距布置的元件分离区域28，位线BL方向上带有条状图案; 以及配置在所述多个存储单元晶体管的阵列的端部的选择晶体管，并且配备有第二浮置栅极82，第二控制栅极122，布置在第二浮置栅极和第二浮置栅极之间的第二层间绝缘膜72 第二控制栅极和将第二浮动栅极连接到第二控制栅极的侧壁栅极6。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005109231A Nonvolatile semiconductor memory, and method for manufacturing same 有权
标题翻译：非线性半导体存储器及其制造方法
公开(公告)号：JP2005109231A
公开(公告)日：2005-04-21
申请号：JP2003342219
申请日：2003-09-30
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKUMA MAKOTO , SATOU ATSUYOSHI
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To solve difficulties in a manufacturing process involving the thinning of floating gates or the use of a dry etch resistant film such as an alumina film as films for insulation between gates.
SOLUTION: In the nonvolatile semiconductor memory and a method for manufacturing the same, the memory comprises a plurality of memory cell transistors arranged in a bit line direction, each having a floating gate, control gate, and a gate insulating film arranged between the floating gate and the control gate, and element isolating regions patterned in stripes in the bit line direction and arranged with a constant pitch in a word line direction. The control gates are arranged continuously in the word line direction, and the insulating films between gates are arranged continuously in the bit line direction and separated with a constant pitch in the word line direction.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：解决涉及浮栅的薄化的制造过程中的困难，或者使用诸如氧化铝膜的耐干蚀刻膜作为栅极之间的绝缘膜。解决方案：在非易失性半导体存储器及其制造方法中，存储器包括沿位线方向排列的多个存储单元晶体管，每个具有浮置栅极，控制栅极和栅极绝缘膜，其布置在浮置栅极和控制栅极以及元件隔离区域，其在位线方向上以条纹形成图案，并且在字线方向上以恒定的间距排列。控制栅极在字线方向上连续排列，并且栅极之间的绝缘膜在位线方向上连续排列，并且在字线方向上以恒定的间距分开。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2008047870A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008047870A
公开(公告)日：2008-02-28
申请号：JP2007155676
申请日：2007-06-12
申请人： Toshiba Corp , 株式会社東芝
发明人： AKAHORI HIROSHI , TAKEUCHI WAKAKO , SATOU ATSUYOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor device in which leakage current through an insulating film disposed between gate electrodes is suppressed to improve electrical reliability.
SOLUTION: A nonvolatile semiconductor device includes a plurality of memory elements formed above a semiconductor substrate in rows and columns, a plurality of bit lines selectively connected with the memory elements in same column direction, a plurality of word lines connected with the memory elements in same row direction. Each memory element includes: a first gate insulating film formed above the semiconductor substrate, a charge accumulation layer formed on the first gate insulating film, a second gate insulating film formed on the charge accumulation layer, and a control electrode formed on the second gate insulating film; and a pair of impurity injection layers formed on the above-described silicon substrate, along the side surfaces of the charge accumulation layer which face each other, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulating film in a cross section along a direction vertical to the bit lines.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种非易失性半导体器件，其中通过设置在栅电极之间的绝缘膜的漏电流被抑制以提高电可靠性。解决方案：非易失性半导体器件包括以行和列形成在半导体衬底之上的多个存储元件，多个与列存储器元件相同的列方向连接的位线，与存储器连接的多条字线元素在同一行方向。每个存储元件包括：形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的电荷累积层，形成在电荷累积层上的第二栅极绝缘膜，以及形成在第二栅极绝缘上的控制电极电影; 以及沿电荷累积层的彼此相对的侧表面形成在上述硅衬底上的一对杂质注入层，其中比率r / d不小于0.5，其中r：曲率半径电荷累积层的上角部或表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘膜的等效氧化物厚度。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007184040A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007184040A
公开(公告)日：2007-07-19
申请号：JP2006001456
申请日：2006-01-06
申请人： Toshiba Corp , 株式会社東芝
发明人： SATOU ATSUYOSHI , SHUDO KEIJI , ARAI FUMITAKA
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which influence of threshold value variation (approximation effect) caused by parasitic capacitance between adjacent memory cells can be removed. SOLUTION: A plurality of memory cells are arranged in a matrix state in a memory cell array 1, the memory cell array 1 has a memory cell MC1 to be read out and memory cells MC2 to MC4 arranged adjacent to the memory cell 1. A determination potential correcting circuit 23 corrects a determination potential based on threshold values of the memory cells MC2 to MC4. A read circuit reads the memory cell MC1 to be read using the corrected determination potential. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种非易失性半导体存储器件，其中可以消除由相邻存储单元之间的寄生电容引起的阈值变化（近似效应）的影响。解决方案：在存储单元阵列1中以矩阵状态布置多个存储单元，存储单元阵列1具有要读出的存储单元MC1和与存储单元1相邻布置的存储单元MC2至MC4 判定电位校正电路23根据存储单元MC2〜MC4的阈值来校正判定电位。读取电路使用校正的确定电位读取要读取的存储单元MC1。版权所有（C）2007，JPO＆INPIT

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