专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2012028420A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012028420A
公开(公告)日：2012-02-09
申请号：JP2010163382
申请日：2010-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： IWAZAWA KAZUAKI , NAGASHIMA YUKINOBU , AKAHORI HIROSHI , NISHIHARA KIYOHITO , KONDO MASAKI , KONDO SHIGEO , ICHIKAWA HISASHI , CHANG YONG-GANG
IPC分类号： H01L21/762 , H01L21/76 , H01L21/8247 , H01L27/08 , H01L27/10 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792
CPC分类号： H01L29/1083 , H01L21/84 , H01L27/11526 , H01L27/11529 , H01L27/1207 , H01L29/66825 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same having an SOI structure which can be formed in simple steps.SOLUTION: The semiconductor device manufacturing method of the present invention is the method in which side faces in parallel with a channel direction of a plurality of gate electrodes provided on a semiconductor substrate are included in as partial inner walls of isolation trenches provided between neighboring gate electrodes. The manufacturing method comprises the steps of: forming first isolation trenches penetrating a conductive film to form gate electrodes to reach the semiconductor substrate; forming a protection film covering side walls of the first isolation trenches including side faces of the gate electrodes; forming second isolation trenches by etching the semiconductor substrate exposed at the bottoms of the first isolation trenches; connecting two first insulator films, which are formed by oxidation of inner faces of the second isolation trenches provided on both sides of the gate electrodes, at locations below respective gate electrodes; and filling the insides of the first trenches with second insulator films.
摘要翻译：要解决的问题：提供一种具有SOI结构的半导体器件及其制造方法，其可以以简单的步骤形成。解决方案：本发明的半导体器件制造方法是其中设置在半导体衬底上的多个栅电极的沟道方向平行的侧面作为隔离沟槽的部分内壁包括在相邻栅电极。该制造方法包括以下步骤：形成贯穿导电膜的第一隔离沟槽，形成栅电极到达半导体衬底; 形成覆盖包括所述栅电极的侧面的所述第一隔离沟槽的侧壁的保护膜; 通过蚀刻在第一隔离沟槽的底部暴露的半导体衬底形成第二隔离沟槽; 连接两个第一绝缘膜，它们通过在栅电极的两侧上设置的第二隔离沟槽的内表面氧化而形成; 并用第二绝缘膜填充第一沟槽的内部。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2010282369A Memory system 审中-公开
标题翻译：记忆系统
公开(公告)号：JP2010282369A
公开(公告)日：2010-12-16
申请号：JP2009134308
申请日：2009-06-03
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO SHIGEO , NARUGE KIYOMI , SHIGYO NAOYUKI
IPC分类号： G06F12/16 , G06F3/08
CPC分类号： G06F11/1044
摘要： PROBLEM TO BE SOLVED: To provide a memory system for ensuring the entire reliability and relaxing a defect level permitted for a single chip. SOLUTION: The memory system includes: a memory chip group that includes n nonvolatile semiconductor memory chips divided and managed for each unit region in a prescribed size and stores an error correction code for a group including a unit region in the other n-1 chips respectively correlated with the unit regions in the unit region of one chip from among the n chips, wherein the chip for storing the error correction code differs for each position in the unit region; and an access destination calculation section for designating a unit region storing the error correction code of the data as a write destination of rewrite data when rewriting the data in the unit region, and designating a unit region storing data before rewriting as a storage destination of a new error correction code. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于确保整个可靠性并放松单个芯片允许的缺陷水平的存储系统。存储器系统包括：存储器芯片组，其包括以规定尺寸为每个单位区域划分和管理的n个非易失性半导体存储器芯片，并且将包括单元区域的组的纠错码存储在另一个n- 1个芯片分别与n个芯片中的一个芯片的单位区域中的单元区域相关，其中用于存储纠错码的芯片对于单位区域中的每个位置而不同; 以及访问目的地计算部分，用于在重写单元区域中的数据时指定存储数据的纠错码的单位区域作为重写数据的写入目的地，并且指定在重写之前存储数据的单位区域作为存储目的地新的纠错码。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2014102868A Nand-type nonvolatile semiconductor memory device 审中-公开
标题翻译： NAND型非易失性半导体存储器件
公开(公告)号：JP2014102868A
公开(公告)日：2014-06-05
申请号：JP2012254752
申请日：2012-11-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO SHIGEO
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3404 , G11C11/5628 , G11C16/0483 , G11C16/3459
摘要： PROBLEM TO BE SOLVED: To improve the reliability of data of a NAND-type nonvolatile semiconductor memory device.SOLUTION: A NAND-type nonvolatile semiconductor device comprises a memory cell array and a control circuit. The memory cell array comprises: memory strings in which a plurality of memory cells are connected in series; word lines which are connected to the plurality of memory cells; and bit lines which are connected to one ends of the memory strings. The control circuit performs: a program operation in which a write voltage is applied to the word lines in a write operation; a verification operation that is performed after the program operation; and a step-up operation in which a voltage, which is obtained by adding a step-up voltage to the write voltage, is set as the write voltage to a memory cell for which it is determined that writing is insufficient, out of the plurality of memory cells. The value of the step-up voltage increases each time the write voltage application operation is performed.
摘要翻译：要解决的问题：提高NAND型非易失性半导体存储器件的数据的可靠性。解决方案：NAND型非易失性半导体器件包括存储单元阵列和控制电路。存储单元阵列包括：多个存储单元串联连接的存储器串; 连接到多个存储单元的字线; 以及连接到存储器串的一端的位线。控制电路执行：在写入操作中向字线施加写入电压的编程操作; 在程序操作之后执行的验证操作; 以及升压操作，其中通过将升压电压加到写入电压上而获得的电压被设置为对确定写入不足的存储单元的写入电压，在多个的记忆细胞。每次执行写入电压施加操作时，升压电压的值都增加。

4. 发明专利

JP2012028419A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012028419A
公开(公告)日：2012-02-09
申请号：JP2010163381
申请日：2010-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： IWAZAWA KAZUAKI , NAGASHIMA YUKINOBU , AKAHORI HIROSHI , NISHIHARA KIYOHITO , KONDO MASAKI , KONDO SHIGEO , ICHIKAWA HISASHI , CHANG YONG-GANG
IPC分类号： H01L21/76 , H01L21/8247 , H01L27/08 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same which can form insulator films inside a microfabricated isolation trench having a high aspect ratio.SOLUTION: The semiconductor device manufacturing method in which side faces in parallel with a channel direction of a plurality of gate electrodes provided on a semiconductor substrate via a gate insulator film are included as partial inner walls of isolation trenches provided between neighboring gate electrodes, comprises the steps of forming protective films covering side faces of the gate electrodes, forming isolation trenches by etching the semiconductor substrate using the gate electrodes with the side faces covered with the protective films as a mask, forming first insulator films by oxidation of surfaces of the isolation trenches to fill the bottom portions of the isolation trenches with the respective first insulator films and forming second insulator films on the first insulator films to fill the upper portions including the side faces of the gate electrodes with the respective second insulator films.
摘要翻译：解决的问题：提供一种半导体器件及其制造方法，该半导体器件及其制造方法可以在具有高纵横比的微加工隔离沟槽内形成绝缘膜。解决方案：包括设置在半导体衬底上的多个栅极的通过栅极绝缘膜设置的与沟道方向平行的半导体器件制造方法包括设置在相邻栅电极之间的隔离沟槽的部分内壁包括以下步骤：形成覆盖栅电极的侧面的保护膜，通过使用覆盖有保护膜的侧面作为掩模的栅电极蚀刻半导体衬底形成隔离沟槽，通过氧化表面形成第一绝缘膜所述隔离沟槽用相应的第一绝缘膜填充所述隔离沟槽的底部，并在所述第一绝缘膜上形成第二绝缘膜，以填充包括所述栅极电极的侧面的上部，并具有相应的第二绝缘膜。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2013161487A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2013161487A
公开(公告)日：2013-08-19
申请号：JP2012019885
申请日：2012-02-01
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO SHIGEO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of narrowing the threshold distribution of memory cells.SOLUTION: According to an embodiment, a nonvolatile semiconductor storage device includes: a plurality of memory cells; a plurality of word lines and a plurality of bit lines that are used for controlling the memory cells. Furthermore, the device includes a control unit that applies a write voltage to a first word line out of the plurality of word line one or more times to write data to within the memory cells on the first word line; and after writing data to within the memory cells on the first word line, applies an additional voltage to the first word line one or more times. In writing to a second word line after writing to the first word line, the control unit writes data within the memory cells on the second word lines, sets the plurality of bit lines to a non-selected state or selected state, and then applies the additional voltage to the second word line.
摘要翻译：要解决的问题：提供能够缩小存储单元的阈值分布的非易失性半导体存储装置。解决方案：根据实施例，非易失性半导体存储装置包括：多个存储单元; 用于控制存储单元的多个字线和多个位线。此外，该装置包括：控制单元，其对多个字线中的第一字线施加写入电压一次或多次以将数据写入到第一字线上的存储单元内; 并且在将数据写入到第一字线上的存储器单元内之前，向第一字线施加一次或多次附加电压。在写入第一字线之后，在写入第二字线时，控制单元将数据写入第二字线内的存储器单元中，将多个位线设置为未选择状态或选择状态，然后将对第二字线的额外电压。

6. 发明专利

JP2012019020A Nonvolatile memory unit 审中-公开
标题翻译：非易失性存储单元
公开(公告)号：JP2012019020A
公开(公告)日：2012-01-26
申请号：JP2010154850
申请日：2010-07-07
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGASHIMA YUKINOBU , AKAHORI HIROSHI , IWAZAWA KAZUAKI , CHANG YONG-GANG , ICHIKAWA HISASHI , KONDO SHIGEO , KONDO MASAKI , NISHIHARA KIYOHITO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883 , H01L27/11521
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory unit having a high voltage endurance between an active region of a substrate and a control gate electrode.SOLUTION: The nonvolatile memory unit has: a substrate having device isolating dielectric trenches; first and second tunnel dielectric films and first and second floating gate electrodes formed on the substrate on both sides of each device isolating trench; an inter-gate dielectric film formed to cover upper surfaces of the first and second floating gate electrodes and to fill at least an upper portion of each device isolating dielectric trench, which is located between the first and second floating gate electrodes and between the first and second tunnel dielectric films; and a control gate electrode formed on the inter-gate dielectric film. The inter-gate dielectric film includes: an electron trap layer made of a first dielectric material having the ability to trap electrons; and first and second dielectric layers made of a second dielectric material smaller than the first material in the ability to trap electrons, and sandwiching the electron trap layer therebetween.
摘要翻译：要解决的问题：提供一种在基板的有源区域和控制栅电极之间具有高耐压性的非易失性存储单元。解决方案：非易失性存储器单元具有：具有器件隔离电介质沟槽的衬底; 第一和第二隧道介电膜以及在每个器件隔离沟槽的两侧上形成在衬底上的第一和第二浮栅; 形成为覆盖第一和第二浮栅的上表面并且填充位于第一和第二浮栅之间以及位于第一和第二浮栅之间的每个器件隔离电介质沟槽的至少上部的栅极间电介质膜第二隧道介电膜; 以及形成在栅极间电介质膜上的控制栅电极。栅极间电介质膜包括：由具有捕获电子的能力的第一电介质材料制成的电子俘获层; 以及由捕获电子的能力小于第一材料的第二电介质材料制成的第一和第二电介质层，并且夹在其间的电子陷阱层。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2011210337A Nonvolatile semiconductor storage device and writing method thereof 审中-公开
标题翻译：非易失性半导体存储器件及其写入方法
公开(公告)号：JP2011210337A
公开(公告)日：2011-10-20
申请号：JP2010079830
申请日：2010-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： HOGYOKU MITSURU , FUKUDA KOICHI , UENO HIROTAKA , KONDO SHIGEO , YAMADA KUNIHIRO , SHIGYO NAOYUKI
IPC分类号： G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To narrow threshold distribution by suppressing write fluctuation in a nonvolatile semiconductor storage device.SOLUTION: When a threshold of a memory cell transistor to be written is less than a first threshold, first writing for applying a first bit line voltage to a bit line is performed. When the threshold of a memory cell transistor to be written is not less than the first threshold and less than a second threshold, second writing for applying a second bit line voltage larger than the first bit line voltage to the bit line is performed. When the threshold of a memory cell transistor to be written is not less than the second threshold and less than a third threshold, third writing for applying a third bit line voltage larger than the second bit line voltage to the bit line is performed.
摘要翻译：要解决的问题：通过抑制非易失性半导体存储装置中的写入波动来窄化阈值分布。解决方案：当要写入的存储单元晶体管的阈值小于第一阈值时，首先写入以将第一位线电压施加到执行位线。当要写入的存储单元晶体管的阈值不小于第一阈值并小于第二阈值时，执行用于将大于第一位线电压的第二位线电压施加到位线的第二写入。当要写入的存储单元晶体管的阈值不小于第二阈值且小于第三阈值时，执行用于将大于第二位线电压的第三位线电压施加到位线的第三写入。

8. 发明专利

JP2011187140A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011187140A
公开(公告)日：2011-09-22
申请号：JP2010053595
申请日：2010-03-10
申请人： Toshiba Corp , 株式会社東芝
发明人： HOGYOKU MITSURU , KONDO SHIGEO
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which can perform writing with high efficiency. SOLUTION: The nonvolatile semiconductor memory device has a plurality of memory cell transistors MT connected in series; selective gate transistors ST2 connected between one ends of the memory cell transistors and source lines, selective gate transistors ST1, connected between the other ends of the memory cell transistors and bit lines; and a control circuit that applies a first voltage to the source lines, applies a second voltage which is higher than the first voltage and whose difference with the first voltage is smaller than a voltage corresponding to a barrier height of a tunnel insulating film, to the bit lines, and performs writing to the memory cell transistor of a writing target by making a conduction state of the adjacent memory cell transistor MT which is positioned between the memory cell transistor MT of the writing target and the source lines and which is adjacent to the memory cell transistor of the writing target, to be weaker than the conducting states of the other memory cell transistors MT. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够以高效率进行写入的非易失性半导体存储器件。解决方案：非易失性半导体存储器件具有串联连接的多个存储单元晶体管MT; 连接在存储单元晶体管和源极线的一端之间的选择栅极晶体管ST2，连接在存储单元晶体管的另一端和位线之间的选择栅极晶体管ST1; 以及控制电路，对源极线施加第一电压，施加比第一电压高且与第一电压的差小于对应于隧道绝缘膜的势垒高度的电压的第二电压，并且通过使位于写入目标的存储单元晶体管MT和源极线之间并且与写入对象相邻的存储单元晶体管MT之间的相邻存储单元晶体管MT的导通状态来执行写入目标的存储单元晶体管的写入写入目标的存储单元晶体管比其它存储单元晶体管MT的导通状态弱。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011141939A Nonvolatile semiconductor memory device and control method thereof 审中-公开
标题翻译：非易失性半导体存储器件及其控制方法
公开(公告)号：JP2011141939A
公开(公告)日：2011-07-21
申请号：JP2010003289
申请日：2010-01-08
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO SHIGEO , NARUGE KIYOMI , MORIKADO MUTSUO , SHIGYO NAOYUKI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To expand a setting range of a threshold voltage of a memory cell by substantially increasing the threshold voltage of the memory cell after program when data is read. SOLUTION: When data is read, a control circuit applies: a first voltage to a control gate of a selected first memory cell transistor in a NAND column; a second voltage different from the first voltage to a second memory cell transistor which is adjacent to a side of a first selection gate transistor of the selected first memory cell transistor; and a third voltage different from the first and second voltages to a third memory cell transistor which is adjacent to a side of a second selection gate transistor of the selected first memory cell transistor. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过在读取数据之后，在程序之后通过显着增加存储单元的阈值电压来扩大存储单元的阈值电压的设置范围。解决方案：当数据被读取时，控制电路将第一电压施加到NAND列中所选择的第一存储单元晶体管的控制栅极; 与所述第一电压不同的第二电压到与所选择的第一存储单元晶体管的第一选择栅晶体管的一侧相邻的第二存储单元晶体管; 以及与第一和第二电压不同的第三电压连接到与所选择的第一存储单元晶体管的第二选择栅晶体管的一侧相邻的第三存储单元晶体管。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JPH07334778A MAINTENANCE MONITOR DEVICE 失效
公开(公告)号：JPH07334778A
公开(公告)日：1995-12-22
申请号：JP12501094
申请日：1994-06-07
申请人： TOSHIBA CORP
发明人： KONDO SHIGEO
IPC分类号： G08B29/00
摘要： PURPOSE:To send a patrol to a corresponding position urgently according to a state by detecting the state of respective positions in facilities to be monitored such as building facilities and plant facilities. CONSTITUTION:A center monitor device 4 has a three-dimensional model storage part which stores a three-dimensional model of the facilities to be monitored, a patrol position three-dimensional model chart generating means which decide positions whose states meet specific patrol conditions among the respective positions as patrol positions and generate a patrol position three-dimensional model chart 13 indicated on the three-dimensional model, and a patrol position transmitting means which sends the generated patrol position three-dimensional model chart 13 to a portable terminal device 5 connected to this center monitor device 4 through a radio line 3. Further, the portable terminal device 4 has a patrol position display means which displays the received patrol position three-dimensional model chart 13 on a display unit in three dimensions.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式