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1. 发明专利

JP5374412B2 Semiconductor memory circuit 有权
公开(公告)号：JP5374412B2
公开(公告)日：2013-12-25
申请号：JP2010039210
申请日：2010-02-24
申请人：ラピスセミコンダクタ株式会社
发明人：伸一村田
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/18 , G11C16/0491 , G11C16/26
摘要： The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier.

2. 发明专利

JP5085934B2 High precision memory read operations for the selection circuit 有权
公开(公告)号：JP5085934B2
公开(公告)日：2012-11-28
申请号：JP2006536517
申请日：2004-01-08
申请人：スパンションエルエルシー
发明人：カンリビン , アクターマイケル , クリーブランドリー , チェンポー−リン
IPC分类号： G11C16/06 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , G11C17/12
CPC分类号： G11C16/0491 , G11C16/24 , G11C16/26

3. 发明专利

JP5057517B2 Semiconductor device and a method of controlling the same 有权
公开(公告)号：JP5057517B2
公开(公告)日：2012-10-24
申请号：JP2007316460
申请日：2007-12-06
申请人：スパンションエルエルシー
发明人：聡高橋
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/28 , G11C16/0475 , G11C16/0491 , G11C16/3431 , G11C16/3436

4. 发明专利

JP2012043520A Nonvolatile semiconductor memory device and driving method thereof 审中-公开
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：JP2012043520A
公开(公告)日：2012-03-01
申请号：JP2010186202
申请日：2010-08-23
申请人： Panasonic Corp , パナソニック株式会社
发明人： TAKAHASHI KEITA
IPC分类号： G11C16/06 , G11C16/04 , G11C17/06
CPC分类号： G11C16/0466 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which has high arrangement efficiency of cells and low current consumption in reading, and furthermore, which can read data at high speed.SOLUTION: A nonvolatile semiconductor memory device includes a first selection transistor 21 whose gate is connected to a first selection word line 23 extending in a column direction, whose source is connected to a first sub bit line 20, and whose drain is connected to a first main bit line 22 extending in a row direction, and a second selection transistor 31 whose gate is connected to a second selection word line 33 extending in the column direction, whose source is connected to a second sub bit line 30, and whose drain is connected to a second main bit line 32 extending in the row direction. A withstand voltage of the second selection transistor 31 is lower than a withstand voltage of the first selection transistor 21.
摘要翻译：要解决的问题：提供一种非易失性半导体存储器件，其在读取时具有高的单元布置效率和低的电流消耗，此外，其可以高速读取数据。解决方案：非易失性半导体存储器件包括：第一选择晶体管21，其栅极连接到在列方向上延伸的第一选择字线23，其源极连接到第一子位线20，并且其漏极连接连接到沿行方向延伸的第一主位线22和第二选择晶体管31，其栅极连接到在列方向上延伸的第二选择字线33，其源极连接到第二子位线30，并且其漏极连接到在行方向上延伸的第二主位线32。第二选择晶体管31的耐受电压低于第一选择晶体管21的耐受电压。版权所有：（C）2012，JPO＆INPIT

6. 发明专利

JP4772429B2 Semiconductor memory device 有权
公开(公告)号：JP4772429B2
公开(公告)日：2011-09-14
申请号：JP2005248286
申请日：2005-08-29
申请人：ルネサスエレクトロニクス株式会社
发明人：和彦真田 , 宏治金森 , 直昭須藤
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7885 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.

7. 发明专利

JP4606239B2 Memory array circuit 有权
公开(公告)号：JP4606239B2
公开(公告)日：2011-01-05
申请号：JP2005127362
申请日：2005-04-26
申请人： Okiセミコンダクタ株式会社
发明人：伸一村田
IPC分类号： G11C16/04 , G11C16/02 , G11C16/06
CPC分类号： G11C16/24 , G11C7/02 , G11C7/18 , G11C16/0491 , G11C2207/002

8. 发明专利

JP2009532820A Reduction of leakage current and program disturb in a flash memory device 审中-公开
公开(公告)号：JP2009532820A
公开(公告)日：2009-09-10
申请号：JP2009504313
申请日：2007-04-05
申请人：スパンションエルエルシー
发明人：ティモシーサーゲイト , クォータンチャン
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/0475 , G11C5/146 , G11C16/04 , G11C16/0491 , G11C16/10 , G11C16/3427 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要：【課題】フラッシュメモリ装置においてリーク電流及びプログラムディスターブを抑制すること。
【解決手段】本発明の実施例に従って構成されたフラッシュメモリシステム３００は、仮想接地方式のアレイ構成（３０２）を採用している。プログラム動作中において、対象メモリセル（７０６）には負の基板電圧が印加され、当該電圧がなければ対象メモリセル（７０６）内を流れてしまうであろうリーク電流を制御または排除する。当該負の基板電圧はまた、対象セルのドレインに対応するビット線（ＢＬ２）の下方に空乏領域（７１４）をより深く拡張することにより、対象セルに隣接するセル（７０８）におけるプログラムディスターブの発生を抑制する。当該負の基板電圧は、ベリファイ動作（プログラムベリファイ、弱プログラムベリファイ、消去ベリファイ）の間にも、対象セル（７０６）に印加され、当該電圧がなければ引き起こされるであろうベリファイ動作中のエラーを抑制または排除する。
【選択図】図８

9. 发明专利

JP2009140576A Semiconductor device and method of controlling the same 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：JP2009140576A
公开(公告)日：2009-06-25
申请号：JP2007316460
申请日：2007-12-06
申请人： Spansion Llc , スパンションエルエルシー
发明人： TAKAHASHI SATOSHI
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/28 , G11C16/0475 , G11C16/0491 , G11C16/3431 , G11C16/3436
摘要： PROBLEM TO BE SOLVED: To improve a data reading stability in a nonvolatile memory. SOLUTION: The semiconductor device includes a plurality of memory cells MC storing data of two bits per one cell; and a first reference cell RC1 and a second reference cell RC2 shared by the plurality of memory cells MC. When program operation for the memory cell MC is performed, program for a program object cell PMC and refresh for a refresh object cell RMC are performed using a threshold of the second reference cell RC2 corresponding to a program state of the memory cell MC to verify. Also, for the second reference cell RC2, program is performed using a first threshold to verify when the program is performed, refresh is performed using a second threshold being lower than the first threshold when refresh is performed. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提高非易失性存储器中的数据读取稳定性。解决方案：半导体器件包括存储每一个单元两位数据的多个存储单元MC; 以及由多个存储单元MC共享的第一参考单元RC1和第二参考单元RC2。当执行存储单元MC的编程操作时，使用对应于存储单元MC的程序状态的第二参考单元RC2的阈值来执行用于程序对象单元PMC的程序和刷新对象单元RMC的刷新以进行验证。此外，对于第二参考单元RC2，使用第一阈值执行程序以验证何时执行程序，当执行刷新时，使用低于第一阈值的第二阈值来执行刷新。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2009123294A Semiconductor nonvolatile memory 审中-公开
标题翻译： SEMICONDUCTOR NONVOLATILE MEMORY
公开(公告)号：JP2009123294A
公开(公告)日：2009-06-04
申请号：JP2007297059
申请日：2007-11-15
申请人： Panasonic Corp , パナソニック株式会社
发明人： KOJIMA MAKOTO
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0491 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To accurately execute reading of a memory cell without discharging respective bit lines before reading, in a semiconductor nonvolatile memory. SOLUTION: In reading the memory cell 03, a bit line BL23 connected to a drain is connected to a voltage source Vd through a main bit line MBL[3] for application of a prescribed voltage, and a bit line BL24 connected to a source is connected to a sense amplifier 71 through a main bit line MBL[0]. At the time, a bit line BL25 is connected to a ground power source GND through a main bit line MBL[1]. That is, since the bit line BL25 near the bit line BL24 of a sense target forcibly becomes a ground level, flow-in of electric charges from it is not caused, flow-in of a current for the bit line BL24 can be prevented. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在半导体非易失性存储器中，准确地执行读取之前的存储单元的读取而不对各个位线进行读取。解决方案：在读取存储单元03时，连接到漏极的位线BL23通过用于施加规定电压的主位线MBL [3]连接到电压源Vd，并且将位线BL24连接到源极通过主位线MBL [0]连接到读出放大器71。此时，位线BL25通过主位线MBL [1]连接到地电源GND。也就是说，由于在感测对象的位线BL24附近的位线BL25强制地成为接地电平，所以不会引起来自其的电荷的流入，可以防止位线BL24的电流的流入。版权所有（C）2009，JPO＆INPIT

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