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1. 发明专利

JP2007227454A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007227454A
公开(公告)日：2007-09-06
申请号：JP2006044072
申请日：2006-02-21
申请人： Toshiba Corp , 株式会社東芝
发明人： ICHIGE MASAYUKI , SAKUMA MAKOTO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , G03F7/20 , H01L21/027 , H01L21/3213 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/0638
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which double exposure is used to realize microfabrication. SOLUTION: When manufacturing a semiconductor device that is provided with a memory cell area including a first pattern, and a peripheral circuit area including a second pattern; a resist film is formed on the area of a substrate including the memory cell area and the peripheral circuit area. Then, when exposing the resist film by multiple exposure including first exposure for forming a latent image corresponding to the first pattern in the resist film on the memory cell area, and second exposure for forming a latent image corresponding to the second pattern in the resist film on the peripheral circuit area; a boundary area 12 between the first and second exposures on the resist film is set on an element isolation area 10' between guard rings 5 and 7, the resists film is developed to form a resist pattern, then the resist pattern is used as a mask, and a substrate to be processed is etched. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，通过双重曝光来实现微细加工。解决方案：制造设置有包括第一图案的存储单元区域和包括第二图案的外围电路区域的半导体器件时; 在包括存储单元区域和外围电路区域的基板的区域上形成抗蚀剂膜。然后，当通过多次曝光（包括用于形成与存储单元区域上的抗蚀剂膜中的第一图案相对应的潜像）的第一曝光来曝光抗蚀剂膜时，以及在抗蚀剂膜中形成与第二图案相对应的潜像的第二曝光在外围电路区域; 将抗蚀剂膜上的第一和第二曝光之间的边界区域12设置在保护环5和7之间的元件隔离区域10'上，将抗蚀剂膜显影以形成抗蚀剂图案，然后将抗蚀剂图案用作掩模，并蚀刻待处理的基板。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2004319948A Non-volatile semiconductor memory 有权
公开(公告)号：JP2004319948A
公开(公告)日：2004-11-11
申请号：JP2003207566
申请日：2003-08-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SHIRATA RIICHIRO , SHIMIZU AKIRA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To reduce parasitic capacity at a periphery of a floating gate, to increase capacity between a control gate and the floating gate, to reduce writing voltage and to realize high integration and high speed. SOLUTION: The floating gate FG is formed on a semiconductor substrate 11 through a gate insulating film GI. Diffusion layers as source or drain regions are formed in the semiconductor substrates 11 positioned on both sides of the floating gate FG. First and second control gates CG driving the floating gate through an inter-gate insulating film IGI are formed on both sides of the floating gate, which correspond to the diffusion layers. COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JP2008103542A Nonvolatile semiconductor storage device and manufacturing method thereof 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2008103542A
公开(公告)日：2008-05-01
申请号：JP2006285088
申请日：2006-10-19
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKUMA MAKOTO
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To make compatible both the lowering of the resistance of a gate electrode using a cobalt silicide and the stabilizing of memory cell transistor characteristics.
SOLUTION: A barrier film 9 composed of a silicon nitride film is not formed on the upper surface and the side wall of a metal semiconductor alloy layer 8 composed of a cobalt silicide film, and formed along the side wall surface of a polycrystal silicon film of a control gate electrode 6, an integrate insulating film 5 and a floating gate electrode 4.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了兼容使用硅化钴降低栅电极的电阻和稳定存储单元晶体管特性。解决方案：在由硅化钴膜构成的金属半导体合金层8的上表面和侧壁上不形成由氮化硅膜构成的阻挡膜9，沿着多晶体的侧壁表面形成控制栅电极6的硅膜，积分绝缘膜5和浮栅电极4.版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007207333A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007207333A
公开(公告)日：2007-08-16
申请号：JP2006023875
申请日：2006-01-31
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA , SATOU ATSUYOSHI , SAKUMA MAKOTO , ENDO MASATO , NISHIHARA KIYOHITO , SHUDO KEIJI , IINO HIROHISA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a nonvolatile semiconductor memory which can realize a small threshold distribution range. SOLUTION: This semiconductor integrated circuit device has a memory cell array including a plurality of blocks, and first non-volatile semiconductor memory cells arranged in the memory cell array and having a first charge storage layer, and second non-volatile semiconductor memory cells arranged close to the first non-volatile semiconductor memory cells in the memory cell array and having a charge storage layer. After normally writing data in the first non-volatile semiconductor memory cells, it normally writes data in the second non-volatile semiconductor memory cells. After normally writing data in the second non-volatile semiconductor memory cells, it writes additional data in the first non-volatile semiconductor memory cells. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够实现小的阈值分布范围的非易失性半导体存储器的半导体集成电路器件。解决方案：该半导体集成电路器件具有包括多个块的存储单元阵列和布置在存储单元阵列中并具有第一电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储器布置在存储单元阵列中靠近第一非易失性半导体存储单元并且具有电荷存储层的单元。在第一非易失性半导体存储单元中正常地写入数据之后，通常在第二非易失性半导体存储单元中写入数据。在第二非易失性半导体存储单元中正常地写入数据之后，它将附加数据写入第一非易失性半导体存储单元。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005354003A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2005354003A
公开(公告)日：2005-12-22
申请号：JP2004175876
申请日：2004-06-14
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA , SAKUMA MAKOTO , IGUCHI SUNAO , TSUNODA HIROAKI , TONOBE HISASHI
IPC分类号： G11C16/06 , G11C16/04 , H01L21/8247 , H01L27/02 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To ensure a space between bit line contacts C, B, and to improve a margin to an electrical short. SOLUTION: A nonvolatile semiconductor memory is provided with memory cell units 55 to 58 which connect in the column direction plural memory cell transistors capable of writing and erasing electrical data; and contacts 64, 65 on an active region which are arranged at both ends of a memory cell unit array serially connecting plural memory cell units in the column direction, and are shared between memory cell units. Plural memory cell unit arrays are arranged in a matrix state so that a distance between the contacts 64, 65 on each active region of each of the memory cell unit arrays arranged in the line direction may be mutually shifted in the line direction by two or more integral multiples of periods of the memory cell units arranged in the line direction. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：确保位线触点C，B之间的空间，并提高电气短路的余量。解决方案：非易失性半导体存储器设置有存储单元单元55至58，其在列方向上连接多个能够写入和擦除电数据的存储单元晶体管; 以及布置在沿列方向串联连接多个存储单元单元的存储单元单元阵列的两端的有源区上的触点64,65，并在存储单元单元之间共享。多个存储单元单元阵列被布置成矩阵状态，使得沿线方向布置的每个存储单元单元阵列的每个有源区上的触点64,65之间的距离可以在线方向上相互偏移两个或更多个在行方向排列的存储单元单元的周期的整数倍。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005116970A Non-volatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2005116970A
公开(公告)日：2005-04-28
申请号：JP2003352663
申请日：2003-10-10
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： H01L21/8247 , G11C11/34 , G11C16/04 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory which can improve operation reliability. SOLUTION: The non-volatile semiconductor memory is equipped with a first semiconductor layer, a laminated-layer gate including a second semiconductor layer which is formed on the first semiconductor layer sandwiching an inter-gate dielectric film and is electrically connected with the first semiconductor layer, a first MOS(metal oxide semiconductor) transistor having a silicide layer formed on a surface of a source and the second semiconductor layer, a charge accumulating layer, a laminated-layer gate including a control gate which is formed on the charge accumulating layer sandwiching the inter-gate dielectric film, and a silicide layer which is formed on a surface of a drain and the control gate. The source includes a second MOS transistor connected with the drain of the first MOS transistor and a side wall dielectric film which is formed on a side wall of the laminated-layer gate of the first MOS transistor. The film thickness of the side wall dielectric film, which is formed on the side wall facing the source of the laminated-layer gate of the first MOS transistor, is larger than 1/2 of the interval between the laminated-layer gates of the first and second MOS transistors. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以提高操作可靠性的非易失性半导体存储器。解决方案：非易失性半导体存储器配备有第一半导体层，包括第二半导体层的层叠栅极，第二半导体层形成在夹着栅极间电介质膜的第一半导体层上，并与第一半导体层，在源极和第二半导体层的表面上形成有硅化物层的第一MOS（金属氧化物半导体）晶体管，电荷蓄积层，包括形成在电荷上的控制栅极的层叠栅极夹持栅极间电介质膜的积层，以及形成在漏极和控制栅极的表面上的硅化物层。源极包括与第一MOS晶体管的漏极连接的第二MOS晶体管和形成在第一MOS晶体管的层叠栅极的侧壁上的侧壁电介质膜。形成在与第一MOS晶体管的层叠层栅极的源极相对的侧壁上的侧壁电介质膜的膜厚大于第一MOS晶体管的层叠栅极之间的间隔的1/2 和第二MOS晶体管。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2010092987A Semiconductor apparatus 审中-公开
标题翻译： SEMICONDUCTOR APPARATUS
公开(公告)号：JP2010092987A
公开(公告)日：2010-04-22
申请号：JP2008259939
申请日：2008-10-06
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKUMA MAKOTO , KUMAGAI YASUSHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： H01L23/53295 , H01L21/76801 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor apparatus reducing a leakage current generated between adjacent wiring and between wiring and an adjacent contact plug, and improving a withstand voltage between them. SOLUTION: An interlayer insulating film 12 is formed on a semiconductor substrate 11, and a contact plug 13 is embedded in the interlayer insulating film 12. An interlayer insulating film 14 is formed on the interlayer insulating film 12. In a groove formed on the interlayer insulating film 14 on the contact plug 13, a wiring layer 15 containing copper is formed. An insulating film 16 is formed in the interlayer insulating film 14 between wiring layers 15. The contact plug 13 has a dent in a part of the top surface, and the insulating layer 16 is formed from the top surface of the interlayer insulating film 14 down to the dent of the contact plug 13. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少相邻布线之间以及布线与相邻接触插塞之间产生的漏电流并提高它们之间的耐电压的半导体装置。解决方案：在半导体衬底11上形成层间绝缘膜12，并且在层间绝缘膜12中嵌入接触塞13.在层间绝缘膜12上形成层间绝缘膜14。在接触塞13上的层间绝缘膜14上形成有铜的布线层15。绝缘膜16形成在布线层15之间的层间绝缘膜14中。接触塞13在顶面的一部分具有凹陷，绝缘层16从层间绝缘膜14的上表面向下接触插头13的凹痕。（C）2010，JPO＆INPIT

8. 发明专利

JP2008091893A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008091893A
公开(公告)日：2008-04-17
申请号：JP2007228882
申请日：2007-09-04
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKUMA MAKOTO , FUTAYAMA TAKUYA
IPC分类号： H01L21/8247 , G03F1/00 , G03F1/68 , G03F7/20 , H01L21/027 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device whose micro-processing rate of patterns in a memory cell array region is not controlled by the patterning capability of a peripheral circuit region. SOLUTION: This semiconductor device comprises a memory cell array region 1, a peripheral circuit region arranged around the memory cell array region, and a border region with a predetermined width arranged between the memory cell array region and the peripheral circuit region. The memory cell array region comprises a cell region including a plurality of nonvolatile semiconductor memory cells, a plurality of straight interconnections arranged extending from the inside of the cell region to the outside region, and a plurality of lower layer interconnections arranged as a lower layer than a plurality of straight interconnections in the border region, which are electrically connected with the plurality of straight interconnections, with a wiring width larger than that of the straight interconnections. The peripheral circuit region comprises a plurality of patterns electrically connected with the plurality of straight interconnections through the plurality of lower layer interconnections. The border region has neither a plurality straight interconnections nor the interconnections of the same layer as the plurality of straight interconnections. The foregoing are the main features of this invention. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其存储单元阵列区域中的图案的微处理速率不受外围电路区域的图案化能力的控制。解决方案：该半导体器件包括存储单元阵列区域1，布置在存储单元阵列区域周围的外围电路区域和布置在存储单元阵列区域和外围电路区域之间的预定宽度的边界区域。存储单元阵列区域包括包括多个非易失性半导体存储单元的单元区域，从单元区域的内部延伸到外部区域的多个直接互连，以及布置为下层的多个下层布线在边界区域中与多个直线互连电连接的多个直线互连，布线宽度大于直线互连的布线宽度。外围电路区域包括通过多个下层互连与多个直接互连电连接的多个图案。边界区域既没有多个直的互连，也没有与多个直的互连相同的层的互连。以上是本发明的主要特征。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007173462A Semiconductor memory device and semiconductor device 有权
标题翻译：半导体存储器件和半导体器件
公开(公告)号：JP2007173462A
公开(公告)日：2007-07-05
申请号：JP2005368148
申请日：2005-12-21
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , SAKUMA MAKOTO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can decrease the noise of selective gate potential in a selective gate transistor and increase stability.
SOLUTION: The semiconductor memory device comprises a memory cell array in which a plurality of cell units having memory cells and selective gate transistors for selecting the memory cells are arranged, upper wiring UL formed on an upper layer of a selective gate line SGSL which is a control gate of the selective gate transistor, and a contact member CP1 formed on the selective gate line SGSL for electrically connecting the selective gate line SGSL with the upper wiring UL. The selective gate line SGSL is formed by laminating a first gate electrode, an inter-gate insulating film, and a second gate electrode in this order, and the inter-gate insulating film has an EI pattern for bringing the first gate electrode into contact with the second gate electrode. Further, the contact member CP1 is disposed on the selective gate line SGSL where the EI pattern is not formed.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够降低选择栅极晶体管中的选择栅极电位的噪声并提高稳定性的半导体存储器件。解决方案：半导体存储器件包括其中布置有具有存储单元的多个单元单元和用于选择存储单元的选择栅晶体管的存储单元阵列，在选择栅极线SGSL的上层上形成的上布线UL 其是选择栅极晶体管的控制栅极，以及形成在选择栅极线SGSL上的用于将选择栅极线SGSL与上部布线UL电连接的接触构件CP1。选择栅极线SGSL通过依次层叠第一栅极电极，栅极间绝缘膜和第二栅极电极而形成，并且栅极间绝缘膜具有用于使第一栅极电极接触的EI图案第二栅电极。此外，接触构件CP1设置在不形成EI图案的选择栅极线SGSL上。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2005268619A Nonvolatile semiconductor memory device and its manufacturing method 有权
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2005268619A
公开(公告)日：2005-09-29
申请号：JP2004080809
申请日：2004-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： H01L21/76 , G11C16/04 , H01L21/28 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/94
CPC分类号： G11C16/0433 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device with an improved operational reliability, and also to provide a method for manufacturing the nonvolatile semiconductor device. SOLUTION: This nonvolatile semiconductor memory is provided with a first MOS transistor and a second MOS transistor. The first MOS transistor is formed on a first device area enclosed by a first device separation area via a first gate insulting film and has a gate width direction edge on the above first device separation area. The second MOS transistor is provided with the second gate electrode which is formed on a secondary device area enclosed by a secondary device separation area via a second gate insulating film whose thickness is double the film thickness of the above first gate insulating film and has a gate width direction edge on the above second device separation area. In addition, the width from the contact position of the above first device separation area and the above first gate insulating film to the edge of the top of the above first element separation area is equal to that from the contact position of the above second device separation area and the above second gate insulating film to the edge of the top of the above second device separation area. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有改进的操作可靠性的非易失性半导体存储器件，并且还提供一种用于制造非易失性半导体器件的方法。解决方案：该非易失性半导体存储器设置有第一MOS晶体管和第二MOS晶体管。第一MOS晶体管形成在由第一器件分离区域经由第一栅极绝缘膜包围的第一器件区域上，并且在上述第一器件分离区域上具有栅极宽度方向边缘。第二MOS晶体管设置有第二栅电极，该第二栅电极形成在由次级器件分离区域包围的次级器件区域上，第二栅极绝缘膜的厚度是上述第一栅极绝缘膜的膜厚度的两倍，并具有栅极宽度方向边缘在上述第二设备分离区域上。此外，从上述第一器件分离区域和上述第一栅极绝缘膜的接触位置到上述第一元件分离区域的顶部的边缘的宽度等于从上述第二器件分离的接触位置的宽度区域和上述第二栅极绝缘膜到上述第二器件分离区域的顶部的边缘。版权所有（C）2005，JPO＆NCIPI

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