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1. 发明专利

JPS62146008A SELECTING CIRCUIT 失效
公开(公告)号：JPS62146008A
公开(公告)日：1987-06-30
申请号：JP28819585
申请日：1985-12-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , ISHIDA JUN , KANEKO KENJI , NAKAGAWA TETSUYA , SATOU TOMORU , MASUMURA SHIGEKI , SUZUKI NORIYASU , HAGIWARA YOSHIMUNE
IPC分类号： H03K17/00 , H03K17/693
摘要： PURPOSE:To make a quick operation possible by selecting one signal in each period from (n-1)-number of input signals taken in from the external and one input signal, which is obtained by feeding back the output of the preceding period, to make it unnecessary to set the time when a decoding signal for control is settled. CONSTITUTION:(n-1)-Number of input signals out of n-number of input signals to be selected are input signals from the external, and remainder one is the signal obtained by feeding back the output of a selecting circuit 409 or a logic circuit 406 following the circuit 409. These n-number of input signals are controlled by a control signal C410 for selection. If any of (n-1)-number of external input signals is not selected, the control signal C410 selects certainly the feedback signal of the state in the preceding period. This feedback signal is selected then to eliminate the no-selection mode, and thereby, the output of the selecting circuit 409 is certainly outputted in each period. Thus, a preceding erroneous selecting signal is cancelled immediately with a correct selecting signal even if the erroneous signal is temporarily selected in the initials stage of synchronization.

2. 发明专利

JPH01119828A MICROPROCESSOR 失效
公开(公告)号：JPH01119828A
公开(公告)日：1989-05-11
申请号：JP27741087
申请日：1987-11-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG
发明人： NOGUCHI YOSHIKI , TSUCHIYA FUMIO , TSUKAMOTO TAKU , MASUMURA SHIGEKI , NAKAMURA HIDEO , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
摘要： PURPOSE:To improve the code efficiency by constructing an instruction system of a microprocessor in a byte unit in which an address operation and an operand operation of an operand are orthogonal to each other. CONSTITUTION:When an address is supplied from a microprocessor, read-out and write of a data are executed through data buses 16, 17 and among the data which are supplied through the data bus H17, an instruction code is sent to an instruction register 10 through prefetch registered 18, 19 in which a prefetched instruction code is stored, and a data for executing an arithmetic processing is inputted to an arithmetic circuit 4. The instruction code is further sent from the instruction register 10 to indirect registers 11-14 for holding an instruction data and a part of the instruction code in the course of executing an instruction. An instruction decoder 1 outputs its address to a microprogram store memory 5.

3. 发明专利

JPS6086859A NONVOLATILE MEMORY DEVICE 失效
公开(公告)号：JPS6086859A
公开(公告)日：1985-05-16
申请号：JP19423683
申请日：1983-10-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAMURA HIDEO , SAWASE TERUMI , MASUMURA SHIGEKI
IPC分类号： H01L27/112 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent the deterioration in characteristics due to re-writing of data by a method wherein the re-writing operation of the non-selective memory element of the memory matrix, to be constituted by a nonvolatile memory element, is prevented. CONSTITUTION:One end of a memory element 111-1n8, connected to the switches which are not turned to ON state simultaneously, is grounded through the intermediary of a normally-ON type MOS transistors (Tr) 41 and 42. When the element 111 is in a write-in state, a write-in current runs into the element 111, and a voltage is generated at both ends of the Tr111. If the drain voltage DELTAV of the Tr41, when a writing-in process is performed, is brought to DELTAV>DELTAVG for the voltage DELTAVG when a word wire is in a non-selective state, the gate and source voltage of an element 121-1n1 is turned to VGS

4. 发明专利

JPS6028098A MEMORY READING CIRCUIT 失效
公开(公告)号：JPS6028098A
公开(公告)日：1985-02-13
申请号：JP13442783
申请日：1983-07-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAMURA HIDEO , MASUMURA SHIGEKI , SAWASE TERUMI
IPC分类号： G11C16/06 , G11C17/00
摘要： PURPOSE:To read a memory at a high speed with a low detecting current by using the drain voltage of a memory element to control the gate voltage of a switching MOSFET. CONSTITUTION:When a memory element 11 is kept on, the drain current of a drain current cut-off MOSFET21 is approximately equal to the ON current of a current detecting MOSFET25 and set at 1/3-1/5 ON current of the element 11. Then the FET21 is cut in response to the reduction of the outputs of inverters 23 and 24. The FET21 has virtually no subthreshold period and performs a high- speed switching performance.

5. 发明专利

JPH0546274A CLOCK DISTRIBUTOR, CLOCK SIGNAL CORRECTION CIRCUIT, ELECTRONIC CIRCUIT SYSTEM, TWO-PHASE CLOCK GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND MICROCOMPUTER 失效
公开(公告)号：JPH0546274A
公开(公告)日：1993-02-26
申请号：JP381292
申请日：1992-01-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO
IPC分类号： G06F1/06 , G06F1/10 , G06F1/12 , G06F15/78
摘要： PURPOSE:To obtain high reliability even when a clock frequency is increased in a system including plural electronic circuits whose operating timings are controlled by two clock signals in which clock pulses are not superimposed. CONSTITUTION:Clock signal correction circuits 131, 132,... which generate the two clock signals phi 1n, phi2n in which the clock pulses are not superimposed from two reference clock signals phi1, phi2 passing a clock transmission path are inserted between the clock transmission path and the electronic circuits 142, 142,... respectively. Thereby, it is possible to distribute the clock signal provided with an appropriate non-overlapping part to the electronic circuits 141, 142,..., which guarantees a stable operation even in a high clock frequency.

6. 发明专利

JPH04195481A SINGLE-CHIP MICROCOMPUTER AND MULTIFUNCTIONAL MEMORY 失效
公开(公告)号：JPH04195481A
公开(公告)日：1992-07-15
申请号：JP32317090
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , AIZAWA TATSUYA , NAITO KAZUO , MIWA YOSHIYUKI , NAKAMURA HIDEO , SAWASE TERUMI , AKAO YASUSHI
IPC分类号： G06F13/38 , G06F15/78 , G11C7/00
摘要： PURPOSE:To select plural data in specific priority order by independently providing a control circuit for realizing necessary functions by storage elements. CONSTITUTION:The multifunctional buffer memory 104 for input/output control is placed between an external port 105 which operates for the synchronization of an asynchronous signal, the setting of the input/output attribute of a terminal, the replacement of input/output sources, etc., and a subprocessor 103, and its various input/output specifications are concentrically controlled for plural input/ output signals. In this case, 10 kinds of memory bits which differ in function are arranged in matrix on the input/output control multifunctional buffer memory 104 and access is enabled in bit units, byte units, and word units with the combination of a column select signal outputted by a column selecting circuit 201 and a row select signal outputted by a row selecting circuit 202. Consequently, input/output interface processing is performed efficiently without any time lag.

7. 发明专利

JPH06150023A MICROCOMPUTER AND SYSTEM THEREOF 失效
公开(公告)号：JPH06150023A
公开(公告)日：1994-05-31
申请号：JP32259892
申请日：1992-11-06
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , FUKADA KAORU , WATABE MITSURU , NOGUCHI YOSHIKI , MATSUBARA KIYOSHI , MOCHIZUKI ISAMU , SUZUKAWA KAZUFUMI , MASUMURA SHIGEKI , AKAO YASUSHI , SAKAKIBARA EIJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
摘要： PURPOSE:To flexibly deal with required system construction by adopting an interface for a dynamic RAM and an interface for a memory such as a static RAM and a peripheral circuit to the microcomputer. CONSTITUTION:This microcomputer is provided with strobe signal output terminals CASH, CASL and RAS for the dynamic RAM and chip select signal output terminals CSO-CS6 for outputting chip select signals parallelly to respective outputs. Then, an address output terminal can output non-multiplexed address signals or address signals multiplexed as needed, and the input/output terminal of data is provided for selectively outputting the address signals so as to cope with the multibus system interface. Thus, the interface for the dynamic RAM and the interface for the memory such as the static RAM and the other peripheral circuit are adopted to the microcomputer.

8. 发明专利

JPH05197546A MICROCOMPUTER AND DIVIDING CIRCUIT 失效
公开(公告)号：JPH05197546A
公开(公告)日：1993-08-06
申请号：JP15452592
申请日：1992-05-21
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： PURPOSE:To decrease program capacity or improve the utilization efficiency of a program memory by employing a fixed length instruction format which is smaller in the number of bits than the maximum length of data words supplied to an instruction executing means. CONSTITUTION:The microcomputer has RISC(reduced instruction set type computer) type architecture and has the fixed length instruction format. When data and instructions are transferred, a bus, e.g. an internal data bus IDB is of 32-bit constitution, but the instructions are in 16-bit fixed length instruction format. Then 16-bit instruction buffers (instruction queue) IRH and IRL store the instructions, one by one, and the instructions are loaded respectively in a single instruction fetch cycle. The instructions are transferred in 32-bit units through the internal data bus IDB and then loaded in an instruction register IR1 through a multiplexer MPX. Then the 16-bit instruction register IR1 holds the instructions present in an instruction decoding stage.

9. 发明专利

JPH04372019A PIPELINE CONTROLLER AND MICROCOMPUTER 失效
公开(公告)号：JPH04372019A
公开(公告)日：1992-12-25
申请号：JP15009991
申请日：1991-06-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI
IPC分类号： G06F9/38
摘要： PURPOSE:To be a variable control content according to a processing content by controlling the execution of the pipeline at every execution step using a software program independent of the processing content that is executed by an electronic circuit. CONSTITUTION:An instruction for the execution of a processing is converted into the first address of a control ROM 104 by a mapping ROM 102. The corresponding microinstruction inputted to the control ROM 104 is read to a microinstruction register 105. The control instruction of a pipeline control field 107 is inputted to a sequence control part 108 and a pipeline control part 109. The control part 108 generates data necessary for the next address control, address selection control, and address conversion control and a control signal 122, supplies them to a selector 10 and the ROM 102, and controls them. The control part 109 generates the pipeline control signal 121 and performs the integrated control of a timing control means necessary for the pipeline execution and the control of the data process.

10. 发明专利

JPH03266035A MICROCOMPUTER 失效
公开(公告)号：JPH03266035A
公开(公告)日：1991-11-27
申请号：JP6425190
申请日：1990-03-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , SAWASE TERUMI , AKAO YASUSHI
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To dynamically change the execution sequence and the execution speed of plural tasks by providing a memory which can execute the programming of the execution sequence of plural tasks, and changing dynamically the address sequence for reading the memory. CONSTITUTION:In an execution task control memory 105 which can execute the programming of the execution sequence of plural tasks, a task execution train and control information for controlling the read-out sequence are stored, and the task corresponding to the task number read out by an execution task read-out register 106 is executed selectively and successively. The read-out address of this execution task control memory 105 is generated by the combining values of a first counter 101 and a second counter 102, and a register 103, and by changing this combining method, plural address sequences corresponding to its combining method are changed dynamically. In such a manner, the execution sequence of plural tasks can be changed dynamically.

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