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1. 发明专利

JPH04195481A SINGLE-CHIP MICROCOMPUTER AND MULTIFUNCTIONAL MEMORY 失效
公开(公告)号：JPH04195481A
公开(公告)日：1992-07-15
申请号：JP32317090
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , AIZAWA TATSUYA , NAITO KAZUO , MIWA YOSHIYUKI , NAKAMURA HIDEO , SAWASE TERUMI , AKAO YASUSHI
IPC分类号： G06F13/38 , G06F15/78 , G11C7/00
摘要： PURPOSE:To select plural data in specific priority order by independently providing a control circuit for realizing necessary functions by storage elements. CONSTITUTION:The multifunctional buffer memory 104 for input/output control is placed between an external port 105 which operates for the synchronization of an asynchronous signal, the setting of the input/output attribute of a terminal, the replacement of input/output sources, etc., and a subprocessor 103, and its various input/output specifications are concentrically controlled for plural input/ output signals. In this case, 10 kinds of memory bits which differ in function are arranged in matrix on the input/output control multifunctional buffer memory 104 and access is enabled in bit units, byte units, and word units with the combination of a column select signal outputted by a column selecting circuit 201 and a row select signal outputted by a row selecting circuit 202. Consequently, input/output interface processing is performed efficiently without any time lag.

2. 发明专利

JPH01296819A PROGRAMMABLE LOGICAL DEVICE 失效
公开(公告)号：JPH01296819A
公开(公告)日：1989-11-30
申请号：JP12808488
申请日：1988-05-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HAYASHI MAKOTO , NAKAMURA HIDEO , SAWASE TERUMI
IPC分类号： H03K19/177
摘要： PURPOSE:To improve the use ratio of an AND array by providing an electrically programmable element at the AND array and a macro call and dividing the word line of the AND array with an AND array dividing switch. CONSTITUTION:The signal from input terminals 91-98 is inputted to 2-bit decoders 81-88, respective inversion and non-inversion signals are generated and inputted to input switches 61 and 62. At this time, from the program condition of an input switch 61, the signal from input terminals 91 and 92 drives word lines 191-194 and the signals from input terminals 93 and 94 are separated from word lines 195-198. From the program condition of input switch 62, the signal from input terminals 95 and 96 is separated from word lines 201-204 and the signals from input terminals 97 and 98 drive work lines 205-206. The inversion of the input terminal 91 and the AND of the input terminal 92 are made into the signal of a product item line 211, and in the same way, the AND of the inversion of the input terminal 92 and the input terminal 91 is made into the signal of a product item line 212 and outputted.

3. 发明专利

JPH01136415A PROGRAMMABLE LOGIC CIRCUIT 失效
公开(公告)号：JPH01136415A
公开(公告)日：1989-05-29
申请号：JP29411387
申请日：1987-11-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HAYASHI MAKOTO , NAKAMURA HIDEO , SAWASE TERUMI
IPC分类号： H03K19/177 , G06F11/22 , G11C29/04
摘要： PURPOSE:To reduce the defective factor to nearly 1/2 or below in comparison with that of an LSI without any test circuit by providing a means checking independently information programmed in an electrically programmable element and checking whether or not a bit memory circuit is operated normally. CONSTITUTION:A test output terminal 94 is provided via a transfer gate 13 comprising a MOS transistor(TR) to a connecting point whose voltage is changed by the information of an E P element 31 programmably electrically in the bit memory circuit 51 and the element 31 is connected to an input of an inverter 40 comprising a complementary MOS circuit driving a switch element 10 via the control element 12. The transfer gate 13 is used to connect only the selected bit memory circuit to the test output line. The control element 12 is used to isolate the element 31 from the bit memory circuit electrically at test. Moreover, the output of the inverter 40 is fed back to the input through a logic inverting circuit to use the test data input terminal and the test output terminal in common at the bit memory circuit test.

4. 发明专利

JPH03266035A MICROCOMPUTER 失效
公开(公告)号：JPH03266035A
公开(公告)日：1991-11-27
申请号：JP6425190
申请日：1990-03-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , SAWASE TERUMI , AKAO YASUSHI
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To dynamically change the execution sequence and the execution speed of plural tasks by providing a memory which can execute the programming of the execution sequence of plural tasks, and changing dynamically the address sequence for reading the memory. CONSTITUTION:In an execution task control memory 105 which can execute the programming of the execution sequence of plural tasks, a task execution train and control information for controlling the read-out sequence are stored, and the task corresponding to the task number read out by an execution task read-out register 106 is executed selectively and successively. The read-out address of this execution task control memory 105 is generated by the combining values of a first counter 101 and a second counter 102, and a register 103, and by changing this combining method, plural address sequences corresponding to its combining method are changed dynamically. In such a manner, the execution sequence of plural tasks can be changed dynamically.

5. 发明专利

JPH03260839A MICROCOMPUTER 失效
公开(公告)号：JPH03260839A
公开(公告)日：1991-11-20
申请号：JP5795390
申请日：1990-03-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , SAWASE TERUMI , AKAO YASUSHI
IPC分类号： G06F9/46
摘要： PURPOSE:To reduce the current consumption in response to the task executing performance with a microcomputer which carries out successively plural tasks in time division by providing a task NOP instruction execute neither task and discontinuing the working of a task executing function for a designated period via the task instruction. CONSTITUTION:The n-bit task number data are successively stored in an executing task control memory 101 in the order of execution for the identification of (m) pieces of tasks. The n-bit data includes at least one code to identify a task NOP in addition to the codes corresponding to the task numbers. The code corresponding to the task NOP is decoded by a NOP deciding circuit 103. This decoding result is identical with the task NOP, the reading operation of a microprogram storing memory 105 is tentatively stopped so as to secure a waiting state where the current consumption is reduced. Simultaneously, the output of a microinstruction reading register 106 is kept invalid for a prescribed period. Thus it is possible to reduce the current consumed by a function circuit whose working is stopped.

6. 发明专利

JPH02103797A SENSE AMPLIFYING CIRCUIT 失效
公开(公告)号：JPH02103797A
公开(公告)日：1990-04-16
申请号：JP25472088
申请日：1988-10-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HAYASHI MAKOTO , NAKAMURA HIDEO , SAWASE TERUMI , MATSUO AKINORI
IPC分类号： G11C17/00 , G11C7/06 , G11C16/06
摘要： PURPOSE:To perform quick operation without precharging by connecting a data line to the input of a current mirror circuit to reduce the variance in voltage of the data line. CONSTITUTION:Such gate voltage is applied to n-type MOS transistors TRs 31 and 32 that a current ID2 proportional to a current ID1 flowing from an output terminal 96 of a current mirror 23 can flow. For example, if a current IM flows to a data line 83 when a word line 81 is selected and a memory cell 71 is set to the conductive state, a current IM1 proportional to the current IM will flow from an output terminal 94 of a current mirror 21. Then, element constants of current mirrors 21 to 23 and n-type MOS TRs 31 to 33 are set to satisfy IM1>ID2, and thereby, the signal in the high level or the low level appears in a sense amplifier output terminals 51 and 52 in accordance with the conductive or non-conductive state of the memory cell. Thus, the variance in voltage of data lines is reduced to perform the quick operation.

7. 发明专利

JPH01274512A SEMICONDUCTOR LOGIC DEVICE 失效
公开(公告)号：JPH01274512A
公开(公告)日：1989-11-02
申请号：JP10254788
申请日：1988-04-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NAKAMURA HIDEO , SAWASE TERUMI , HAYASHI MAKOTO
IPC分类号： H01L21/82 , H03K19/177
摘要： PURPOSE:To write or rewrite the logic structure electrically without increasing number of components by preparing a wire enabling signal propagation exclusively or in time division independently of components of a semiconductor logic device so as to attain high speed signal propagation of discrete logic components. CONSTITUTION:NOR arrays 11, 12, 31, 32 comprising nonvolatile recording components writable electrically are arranged to a programmable logic device, logic cell arrays 211 to 42m are provided to the arrays 11, 21, 31, 32 are two- way switch elements 51, 52 are arranged between the arrays 11 to 12 and 31 to 32. NOR arrays 11, 21, 31, 32 are formed among plural input lines I1 to I5 and plural optional output lines O1 to O11, the input lines I1 to I5 and the output lines O1 to O11 are made orthogonal and nonvolatile elements rewritable or writable electrically are arranged to cross points.

8. 发明专利

JPH0668684A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0668684A
公开(公告)日：1994-03-11
申请号：JP3927091
申请日：1991-02-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ITO HISANORI , MASUMURA SHIGEKI , NAKAMURA HIDEO , HAYASHI MAKOTO , SAWASE TERUMI , MATSUBARA KIYOSHI , AKAO YASUSHI
IPC分类号： G06F7/00 , G06F15/78 , G11C11/417 , G11C16/06 , G11C17/00
摘要： PURPOSE:To reduce current consumption for reading operation, even if access time of a memory cell of which access time is slow is not considered and variation of access time actually varied is comparatively large depending on selected memory cells. CONSTITUTION:In operation for reading data of memory cells M1-M8, a state in which data is actually read out from memory cells M9-M12 as a discriminating bit is detected by a detecting circuit 11, current stopping circuits 13 and 14 are operated synchronizing with it, and sense amplifiers 6a-6c is made non- activation. Also, all word lines W1-W4 are forced to set to a low level, and all memory cells are controlled in non-selection state. Thereby, a stationary current flowing to a memory is stopped. Therefore, a stationary current flowing to a memory is stopped with fast timing when access time is fast, and stopped with slow timing when access time is slow, then current consumption is reduced in actual operation.

9. 发明专利

JPH03222043A MICRO PROCESSOR AND ITS PROGRAM DEVELOPMENT DEVICE 失效
公开(公告)号：JPH03222043A
公开(公告)日：1991-10-01
申请号：JP1599190
申请日：1990-01-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO YUJI , SAWASE TERUMI , AKAO YASUSHI , MASUMURA SHIGEKI
IPC分类号： G06F9/46 , G06F9/48 , G06F15/78
摘要： PURPOSE:To simplify the designation and switching of a task execution order by providing an address register selection means which has a means storing the plural selection orders of address registers and selecting the specified selection order. CONSTITUTION:The address register selection means 145 stores plural selection orders of the address registers in a control memory 150, and an address pointer 160 selects one among the designation of plural address selection orders, which is stored in the memory 150, in response to an external signal 161 and temporarily stores having read data in a micro instruction register 151. The address selection circuit 190 decides the address register to be selected by an address register selection instruction from the memory 150, the address register selection instruction from an external signal 171 and the designation of priority from an external signal 181, and outputs a control signal 191 to a subsequent address register group 140. Consequently, the task execution order can easily be designated and switched as against application different in the task execution orders.

10. 发明专利

JPH03147020A DATA PROCESSOR 失效
公开(公告)号：JPH03147020A
公开(公告)日：1991-06-24
申请号：JP28298389
申请日：1989-11-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO YUJI , SAWASE TERUMI , AKAO YASUSHI , MASUMURA SHIGEKI , AIZAWA TATSUYA
IPC分类号： G06F9/26
摘要： PURPOSE:To freely select the odd number and even number of a subsequent address and to control the number of program steps after assembly by setting an address designated in a control storage device to be the subsequent address as it is when a condition is realized. CONSTITUTION:Data designated in an arithmetic circuit control designation part 18 and an input/output control designation part 19 are read from the control storage device 1. An operation instruction is executed in an arithmetic circuit 2 by the control of having read data, and accordingly state variables such as a carry flag and a zero flag are generated. An input port number is selected in a port 7 by the control of data which is read from the input/output control designation part 19, and data from an external part is inputted. The state variables from the arithmetic circuit 2 and input data from the port are transferred to a branching deciding circuit 3. The circuit 3 decides the realization of a branching condition by data from a branching condition selection designation part 11.

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